CY7C1370D
CY7C1372D
18-Mbit (512 K × 36/1 M × 18) Pipelined
SRAM with NoBL™ Architecture
18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
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Pin-compatible and functionally equivalent to ZBT™
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Supports 250-MHz bus operations with zero wait states
❐ Available speed grades are 250, 200, and 167 MHz
■
Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
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Fully registered (inputs and outputs) for pipelined operation
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Byte write capability
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3.3 V core power supply (VDD)
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3.3 V/2.5 V I/O power supply (VDDQ)
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Fast clock-to-output times
❐ 2.6 ns (for 250 MHz device)
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Clock enable (CEN) pin to suspend operation
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Synchronous self-timed writes
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Available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free
and non Pb-free 65-ball FBGA package
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IEEE 1149.1 JTAG-compatible boundary scan
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Burst capability – linear or interleaved burst order
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“ZZ” sleep mode option and stop clock option
The CY7C1370D and CY7C1372D are 3.3 V, 512 K × 36 and
1 M × 18 synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL logic, respectively. They are designed to
support unlimited true back-to-back read/write operations with
no wait states. The CY7C1370D and CY7C1372D are equipped
with the advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1370D and CY7C1372D are pin compatible and
functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1370D and BWa–BWb for CY7C1372D)
and a write enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Description
250 MHz
200 MHz
167 MHz
Unit
2.6
350
70
Maximum access time
Maximum operating current
Maximum CMOS standby current
3.0
300
70
3.4
275
70
ns
mA
mA
Errata: For information on silicon errata, see “Errata” on page 30. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05555 Rev. *S
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198 Champion Court
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San Jose, CA 95134-1709
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408-943-2600
Revised November 17, 2014
