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HY628100ALG-70
HY628100A Series 128Kx8bit CMOS SRAM DESCRIPTION FEATURES The HY628100A is a high speed, low power and 1M bit CMOS Static Random Access Memory organized as 131,072 words by 8bit. The HY628100A uses high performance CMOS process technology and designed for high speed low power circuit technology. It is particulary well suited for used in high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0V. • Fully static operation and Tri-state output • TTL compatible inputs and outputs • Battery backup(L/LL-part) - 2.0V(min) data retention • Standard pin configuration - 32pin 525mil SOP - 32pin 8x20mm TSOP-I(Standard) Product Voltage Speed Operation No (V) (ns) Current(mA) HY628100A 5.0 55/70/85 10 Comment : 50ns is available with 30pF test load. Standby Current(uA) L LL 1mA 100 20 Temperature (°C) 0~70 PIN CONNECTION Vcc A15 CS2 /WE A13 A8 A9 A11 /OE A10 /CS1 I/O8 I/O7 I/O6 I/O5 I/O4 A13 /WE CS2 A15 Vcc NC A16 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 32 /OE 30 29 28 27 26 25 24 11 12 13 14 15 16 /CS1 DQ8 DQ7 DQ6 DQ5 DQ4 Vss DQ3 22 21 20 19 18 17 DQ1 A0 A1 A2 A3 TSOP-I(Standard) Pin Function Chip Select 1 Chip Select 2 Write Enable Output Enable Address Input Data Input/Output Power(5.0V) Ground ROW DECODER A0 A16 /CS1 CS2 /OE /WE MEMORY ARRAY 1024x1024 I/O1 OUTPUT BUFFER Pin Name /CS1 CS2 /WE /OE A0 ~ A16 I/O1 ~ I/O8 Vcc Vss BLOCK DIAGRAM SENSE AMP PIN DESCRIPTION WRITE DRIVER SOP A11 A9 COLUMN DECODER 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ADD INPUT BUFFER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I/O8 CONTROL LOGIC NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.05 /Feb.99 Hyundai Semiconductor
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