MACH 4 CPLD Family
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Adv
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e In Family
form
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High Performance EE CMOS
Programmable Logic
FEATURES
x High-performance, EE CMOS 3.3-V & 5-V CPLD families
x Flexible architecture for rapid logic designs
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— Excellent First-Time-FitTM and refit feature
— SpeedLockingTM performance for guaranteed fixed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
High speed
— 5.0ns tPD Commercial and 7.5ns tPD Industrial
— 182MHz fCNT
32 to 512 macrocells; 32 to 768 registers
44 to 352 pins in PLCC, PQFP, TQFP, BGA, or fpBGA packages
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-FriendlyTM inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
Advanced EE CMOS process provides high-performance, cost-effective solutions
Supported by Vantis DesignDirectTM software for rapid logic development
— Supports HDL design methodologies with results optimized for Vantis
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
Vantis and third-party hardware programming support
— VantisPROTM (formerly known as MACHPRO®) software for in-system programmability
support on PCs and automated test equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
Publication# 17466
Amendment/0
Rev: J
Issue Date: May 1999
