GAL6001
Features
Functional Block Diagram
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 30ns Maximum Propagation Delay
— 27MHz Maximum Frequency
— 12ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS® Advanced CMOS Technology
ICLK
INPUT
CLOCK
2
{
14
11
23
ILMC
IOLMC
RESET
INPUTS
2-11
AND
OUTPUT
ENABLE
• LOW POWER CMOS
— 90mA Typical Icc
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
14
D
23
OLMC
E
OR
0
D
7
BLMC
{ OUTPUTS
14 - 23
E
• UNPRECEDENTED FUNCTIONAL DENSITY
— 78 x 64 x 36 FPLA Architecture
— 10 Output Logic Macrocells
— 8 Buried Logic Macrocells
— 20 Input and I/O Logic Macrocells
OCLK
OUTPUT
CLOCK
Macrocell Names
ILMC
• HIGH-LEVEL DESIGN FLEXIBILITY
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL®
and FPLA Devices
INPUT LOGIC MACROCELL
IOLMC I/O LOGIC MACROCELL
BLMC
OLMC
• APPLICATIONS INCLUDE:
— Sequencers
— State Machine Control
— Multiple PLD Device Integration
BURIED LOGIC MACROCELL
OUTPUT LOGIC MACROCELL
Pin Names
I0 - I10
Using a high performance E2CMOS technology, Lattice
Semiconductor has produced a next-generation programmable
logic device, the GAL6001. Having an FPLA architecture, known
for its superior flexibility in state-machine design, the GAL6001
offers a high degree of functional integration and flexibility in a 24pin, 300-mil package.
I/O/Q
BIDIRECTIONAL
INPUT CLOCK
VCC
POWER (+5)
OCLK
Description
INPUT
ICLK
OUTPUT CLOCK
GND
GROUND
Pin Configuration
DIP
PLCC
4
I
I/O/Q
28
I
25
GAL6001
23
I/O/Q
I
I/O/Q
I
6
I/O/Q
GAL
6001
I/O/Q
I/O/Q
18
I/O/Q
NC
21
11
I/O/Q
I/O/Q
OCLK
GND
16
NC
14
I
I
12
19
18
I
I/O/Q
I
I/O/Q
I/O/Q
Top View
9
I
I
I/O/Q
I/O/Q
NC
I
Vcc
I/O/Q
I
26
5
7
24
I
I/O/Q
NC
2
I
Advanced features that simplify programming and reduce test time,
coupled with E2CMOS reprogrammable cells, enable 100% AC, DC,
programmability, and functionality testing of each GAL6001 during
manufacture. As a result, Lattice Semiconductor delivers 100% field
programmability and functionality of all GAL products. In addition,
100 erase/write cycles and data retention in excess of 20 years are
specified.
1
I
Vcc
I
I
I/ICLK
I/ICLK
The GAL6001 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
I
I/O/Q
I/O/Q
I
I/O/Q
I/O/Q
I
GND
12
13
OCLK
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
High Performance E2CMOS FPLA
Generic Array Logic™
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
6001_02
1
July 1997
