GAL6002
Features
Functional Block Diagram
ICLK
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 15ns Maximum Propagation Delay
— 75MHz Maximum Frequency
— 6.5ns Maximum Clock to Output Delay
— TTL Compatible 16mA Outputs
— UltraMOS® Advanced CMOS Technology
INPUT
CLOCK
2
14
11
{
23
ILMC
IOLMC
AND
RESET
INPUTS
2-11
OUTPUT
ENABLE
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
— 90mA Typical Icc
14
• E2 CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
D
23
OLMC
E
OR
0
D
7
BLMC
{ OUTPUTS
14 - 23
E
OCLK
• UNPRECEDENTED FUNCTIONAL DENSITY
— 78 x 64 x 36 FPLA Architecture
— 10 Output Logic Macrocells
— 8 Buried Logic Macrocells
— 20 Input and I/O Logic Macrocells
Macrocell Names
• HIGH-LEVEL DESIGN FLEXIBILITY
— Asynchronous or Synchronous Clocking
— Separate State Register and Input Clock Pins
— Functional Superset of Existing 24-pin PAL®
and FPLA Devices
BLMC
BURIED LOGIC MACROCELL
OLMC
OUTPUT
CLOCK
OUTPUT LOGIC MACROCELL
ILMC
INPUT LOGIC MACROCELL
IOLMC I/O LOGIC MACROCELL
PinNames
• APPLICATIONS INCLUDE:
— Sequencers
— State Machine Control
— Multiple PLD Device Integration
I0 - I10
I/O/Q
BIDIRECTIONAL
INPUT CLOCK
VCC
POWER (+5V)
OCLK
Description
INPUT
ICLK
OUTPUT CLOCK
GND
GROUND
Pin Configuration
Having an FPLA architecture, the GAL6002 provides superior
flexibility in state-machine design. The GAL6002 offers the highest
degree of functional integration, flexibility, and speed currently
available in a 24-pin, 300-mil package. E2CMOS technology offers
high speed (<100ms) erase times, providing the ability to reprogram
or reconfigure the device quickly and efficiently.
DIP
PLCC
4
I
I/O/Q
28
I/O/Q
NC
2
Vcc
I/ICLK
I
The GAL6002 has 10 programmable Output Logic Macrocells
(OLMC) and 8 programmable Buried Logic Macrocells (BLMC). In
addition, there are 10 Input Logic Macrocells (ILMC) and 10
I/O Logic Macrocells (IOLMC). Two clock inputs are provided for
independent control of the input and output macrocells.
I
I/ICLK
26
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacturing. As a result, Lattice
Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles
and data retention in excess of 20 years are specified.
I/O/Q
I/O/Q
GAL
6002
I/O/Q
7
23
GAL6002
9
Top View
21
I/O/Q
I
I
I/O/Q
I
NC
25
I
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I/O/Q
11
I/O/Q
OCLK
I/O/Q
19
18
16
NC
14
I
I
12
GND
I
Vcc
I/O/Q
5
NC
I
24
I
I
I
1
I
I/O/Q
I/O/Q
6
I/O/Q
18
I/O/Q
I
GND
I/O/Q
12
13
OCLK
Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability.
www.latticesemi.com/sales/discontinueddevicessales.cfm
High Performance E2CMOS FPLA
Generic Array Logic™
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
6002_02
1
July 1997
