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GAL22LV10Z-25QJ

製品説明
仕様・特性

Discontinued Product (PCN #02-06). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm GAL22LV10Z GAL22LV10ZD Low Voltage, Zero Power E2CMOS PLD Features Functional Block Diagram • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — Interfaces with Standard 5V TTL Devices — 50µA Typical Standby Current (100µA Max.) — 40mA Typical Active Current (55mA Max.) — Input Transition Detection on GAL22LV10Z — Dedicated Power-down Pin on GAL22LV10ZD RESET I/CLK 8 OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q I 10 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 15 ns Maximum Propagation Delay — Fmax = 71.4MHz — UltraMOS® Advanced CMOS Technology I 12 • COMPATIBLE WITH STANDARD 22V10 DEVICES — Fully Function/Fuse-Map/Parametric Compatible with Bipolar and CMOS 22V10 Devices PROGRAMMABLE AND-ARRAY (132X44) I/DPP* I • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100ms) — 20 Year Data Retention I I I • TEN OUTPUT LOGIC MACROCELLS — Maximum Flexibility for Complex Logic Designs 14 16 16 14 I • PRELOAD AND POWER-ON RESET OF REGISTERS — 100% Functional Testability 12 I • APPLICATIONS INCLUDE: — Battery Powered Systems — DMA Control — State Machine Control 10 I 8 • ELECTRONIC SIGNATURE FOR IDENTIFICATION I PRESET *GAL22LV10ZD Only Description Pin Configuration The GAL22LV10Z and GAL22LV10ZD, at 15ns maximum propagation delay time and 100µA standby current, combine 3.3V CMOS process technology with Electrically Erasable (E2) floating gate technology to provide the best PLD solution to support today's new 3.3V systems. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. 4 The generic 22V10 architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL22LV10Z uses Input Transition Detection (ITD) to put the device into standby mode and is fully function/fuse map/ parametric compatible with standard bipolar and CMOS 22V10 devices. The GAL22LV10ZD utilizes a Dedicated Power-down Pin (DPP) to put the device into standby mode. I/DPP Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor is able to deliver 100% field programmability and functionality of all GAL® products. In addition,100 erase/rewrite cycles and data retention in excess of 20 years are specified. I 2 I/O/Q 28 I/O/Q Vcc I/CLK NC I I PLCC 26 5 25 7 GAL22LV10Z GAL22LV10ZD 23 9 Top View 21 I I I/O/Q NC I I/O/Q I/O/Q NC I I/O/Q I/O/Q 11 I/O/Q I I/O/Q 16 NC GND 14 I I 12 19 18 I/O/Q Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 22lv10zd_02 1 July 1997

ブランド

LATTICE

会社名

Lattice Semiconductor Corporation

本社国名

U.S.A

事業概要

主力製品は、FPGA(Field-Programmable Gate Array)、CPLD(Complex Programmable Logic Device)、プログラマブルパワーマネジメント製品である。 FPGAの世界シェアはザイリンクス、アルテラに次いで第3位である。 半導体ベンダーのため、自社で生産ラインは保有していない。製造は富士通セミコンダクターなどで行っている。

供給状況

 
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