128Mb: x16, x32
MOBILE SDRAM
SYNCHRONOUS
DRAM
MT48G8M16LFFF, MT48G8M16LFF4, MT48LC8M16LFFF,
MT48LC8M16LFF4, MT48V8M16LFF4, MT48V8M16LFFF
MT48LC4M32LFFC, MT48LC4M32LFF5, MT48V4M32LFFC,
MT48V4M32LFF5
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/dramds
Features
Figure 1: Pin Assignment (Top View)
54-Ball FBGA
• Temperature Compensated Self Refresh (TCSR)
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT auto
precharge, and Auto Refresh Modes
• Self Refresh Mode; standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Partial Array Self Refresh power-saving mode
OPTIONS
• VDD/VDDQ
3.3V/3.3V
3.0V/3.0V1
2.5V/2.5V – 1.8V
• Configurations
8 Meg x 16 (2 Meg x 16 x 4 banks)
4 Meg x 32 (1 Meg x 32 x 4 banks)
• Package/Ball out
54-ball FBGA (8mm x 9mm)2
54-ball FBGA (8mm x 9mm)2 Lead-Free
54-ball VFBGA (8mm x 8mm)2
54-ball VFBGA (8mm x 8mm)2 Lead-Free
90-ball FBGA (11mm x 13mm)3
90-ball FBGA (11mm x 13mm)3 Lead-Free
90-ball VFBGA (8mm x 13mm)3
90-ball VFBGA (8mm x 13mm)3 Lead-Free
• Timing (Cycle Time)
8ns @ CL = 3 (125 MHz)
10ns @ CL = 3 (100 MHz)
• Temperature
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Extended (-25°C to +75°C)
1
VSS
DQ15
B
DQ14
C
7
8
9
VSSQ
VDDQ
DQ0
VDD
DQ13
VDDQ
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS#
RAS#
WE#
G
NC/A12
A11
A9
BA0
BA1
CS#
H
A8
A7
A6
A0
A1
A10
J
LC
G
V
3
A
MARKING
2
4
5
6
VSS
A5
A4
A3
A2
VDD
Top View
(Ball Down)
8M16
4M32
8 Meg x 16
2 Meg x 16 x 4 banks 1 Meg x 32 x 4 banks
Configuration
FF
BF
F4
B4
FC
BC
F5
B5
4 Meg x 32
4K
4K
Row Addressing
4K (A0–A11)
4K (A0–A11)
Bank Addressing
4 (BA0, BA1)
4 (BA0, BA1)
Column
Addressing
512 (A0–A8)
256 (A0–A7)
Refresh Count
Part Number Example:
Table 1:
-8
-10
MT48V8M16LFFF-8
Key Timing Parameters
ACCESS TIME
SPEED
CLOCK
GRADE FREQUENCY
None
IT
XT
-8
-10
-8
-10
-8
-10
NOTE:
1. Check with factory for configuration and availability.
2. x16 Only.
3. x32 Only.
125 MHz
100 MHz
100 MHz
83 MHz
50 MHz
40 MHz
CL=1*
CL=2*
CL=3*
tRCD
tRP
–
–
–
–
19ns
22ns
–
–
8ns
8ns
–
–
7ns
7ns
–
–
–
–
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
20ns
*CL = CAS (READ) latency
09005aef8071a76b
MobileY95W_3V_1.fm - Rev. H 10/03 EN
1
©2001 Micron Technology, Inc. All rights reserved.
