NT5DS32M4AT
NT5DS16M8AT
128Mb Double Data Rate SDRAM
Features
• DLL aligns DQ and DQS transitions with CK transitions,
also aligns QFC transitions with CK during Read cycles
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2, 2.5
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 15.6µs Maximum Average Periodic Refresh
Interval
• Supports t RAS lockout feature
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = 2.5V ± 0.2V
• VDD = 2.5V ± 0.2V
• -7K parts support PC2100 modules.
-75B parts support PC2100 modules
-8B parts support PC1600 modules
CAS Latency and Frequency
Maximum Operating Frequency (MHz)*
DDR266A
DDR266B
DDR200
(-7K)
(-75B)
(-8B)
2
133
100
100
2.5
143
133
125
* Values are nominal (exact tCK should be used).
CAS Latency
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is centeraligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 134,217,728 bits. It is
internally configured as a quad-bank DRAM.
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
The 128Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 128Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edgealigned with data for Reads and center-aligned with data for
Writes.
Note: The functionality described and the timing specifications included in this data sheet are for the DLL
Enabled mode of operation.
The 128Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
REV 1.0
05/2001
1
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
