1Gb: x4, x8, x16 DDR3 SDRAM
Features
DDR3 SDRAM
MT41J256M4 – 32 Meg x 4 x 8 banks
MT41J128M8 – 16 Meg x 8 x 8 banks
MT41J64M16 – 8 Meg x 16 x 8 banks
Options1
Features
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Marking
• Configuration
– 256 Meg x 4
– 128 Meg x 8
– 64 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (8mm x 11.5mm) Rev. G
– 78-ball (8mm x 10.5mm) Rev. J
• FBGA package (Pb-free) – x16
– 96-ball (8mm x 14mm) Rev. G
– 96-ball (8mm x 14mm) Rev. J
• Timing – cycle time
– 938ps @ CL = 14 (DDR3-2133)
– 1.07ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
• Operating temperature
– Commercial (0°C ≤ T C ≤ +95°C)
– Industrial (–40°C ≤ T C ≤ +95°C)
• Revision
VDD = V DDQ = 1.5V ±0.075V
1.5V center-terminated push/pull I/O
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
Programmable CAS READ latency (CL)
POSTED CAS ADDITIVE latency (AL)
Programmable CAS WRITE latency (CWL) based on
tCK
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
TC of 0°C to 95°C
– 64ms, 8192 cycle refresh at 0°C to 85°C
– 32ms, 8192 cycle refresh at 85°C to 95°C
Self refresh temperature (SRT)
Automatic self refresh (ASR)
Write leveling
Multipurpose register
Output driver calibration
Note:
256M4
128M8
64M16
JP
DA
JT
TW
-093
-107
-125
-15E
-187E
None
IT
:G / :J
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
Table 1: Key Timing Parameters
Speed Grade
Data Rate (MT/s)
Target tRCD-tRP-CL
-0931, 2, 3, 4
2133
14-14-14
13.09
13.09
13.09
-1071, 2, 3
1866
13-13-13
13.91
13.91
13.91
1, 2
tRCD
(ns)
tRP
(ns)
CL (ns)
1600
11-11-11
13.75
13.75
13.75
-15E 1
1333
9-9-9
13.5
13.5
13.5
-187E
1066
7-7-7
13.1
13.1
13.1
-125
Notes:
1.
2.
3.
4.
Backward compatible to 1066, CL = 7 (-187E).
Backward compatible to 1333, CL = 9 (-15E).
Backward compatible to 1600, CL = 11 (-125).
Backward compatible to 1866, CL = 13 (-107).
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. N 11/14 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
