256Mb
DDR SDRAM
Key Features
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM/DM for write masking only
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
• Maximum burst refresh cycle : 8
• 60 Ball FBGA package
ORDERING INFORMATION
Part No.
Org.
K4H560438D-GC(L)B3
K4H560438D-GC(L)A2
Interface
Package
SSTL2
60 ball FBGA
SSTL2
60 ball FBGA
SSTL2
60 ball FBGA
B3(DDR333@CL=2.5)
64M x 4
K4H560438D-GC(L)B0
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
K4H560838D-GC(L)B3
K4H560838D-GC(L)A2
Max Freq.
B3(DDR333@CL=2.5)
32M x 8
A2(DDR266@CL=2)
K4H560838D-GC(L)B0
B0(DDR266@CL=2.5)
K4H561638D-GC(L)B3
B3(DDR333@CL=2.5)
K4H561638D-GC(L)A2
16M x 16
K4H561638D-GC(L)B0
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Operating Frequencies
- B3(DDR333)
- A2(DDR266A)
- B0(DDR266B)
Speed @CL2
133MHz
133MHz
100MHz
Speed @CL2.5
166MHz
133MHz
133MHz
*CL : Cas Latency
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Rev. 2.2 Mar. ’03
