K4F660411D, K4F640411D
CMOS DRAM
16M x 4bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 16,777,216 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time(-50 or -60), package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 16Mx4 Fast
Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption
and high reliability.
FEATURES
• Fast Page Mode operation
• Part Identification
- K4F660411D-JC(5.0V, 8K Ref.)
- K4F640411D-JC(5.0V, 4K Ref.)
- K4F660411D-TC(5.0V, 8K Ref.)
- K4F640411D-TC(5.0V, 4K Ref.)
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• TTL(5.0V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Active Power Dissipation
• Available in Plastic SOJ and TSOP(II) packages
Unit : mW
• +5.0V±10% power supply
Speed
8K
4K
-50
495
660
-60
440
605
• Refresh Cycles
Refresh
cycle
K4F660411D*
FUNCTIONAL BLOCK DIAGRAM
Normal
8K
K4F640411D
Refresh time
4K
64ms
RAS
CAS
W
* Access mode & RAS only refresh mode
: 8K cycle/64ms
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms
Control
Clocks
Refresh Timer
Row Decoder
Refresh Control
Refresh Counter
• Performance Range
Speed
tRAC
tCAC
tRC
tPC
-50
50ns
13ns
90ns
35ns
-60
60ns
15ns
110ns
40ns
A0~A12
(A0~A11)*1
Col. Address Buffer
Memory Array
16,777,216 x 4
Cells
Row Address Buffer
A0~A10
(A0~A11)*1
Vcc
Vss
VBB Generator
Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Sense Amps & I/O
Part
NO.
Data in
Buffer
DQ0
to
DQ3
Data out
Buffer
OE