Preliminary Information
Direct RDRAM for Short Channel
128/144-Mbit (256Kx16/18x32s-C)
®
RAMBUS
Overview
The Rambus Direct RDRAM™ is a general purpose
high-performance memory device suitable for use in a
broad range of applications including communications, graphics, video, and any other application where
high bandwidth and low latency are required.
The 128/144-Mbit Direct Rambus DRAMs (RDRAM)
are extremely high-speed CMOS DRAMs organized as
8M words by 16 or 18 bits. The use of Rambus
Signaling Level (RSL) technology permits 800MHz to
1066MHz transfer rates while using conventional
system and board design technologies. Direct RDRAM
devices are capable of sustained data transfers at 0.94
ns per two bytes (7.5ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the
highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The
separate control and data buses with independent row
and column control yield over 95% bus efficiency. The
Direct RDRAM's 32 banks support up to four simultaneous transactions.
System oriented features for mobile, graphics and
communications include power management, byte
masking, and x18 organization. The two data bits in the
x18 organization are general and can be used for additional storage and bandwidth or for error correction.
Figure 1: Direct RDRAM CSP Package
The 128/144-Mbit Direct RDRAMs are offered in a
horizontal center-bond fanout CSP or standard CSP
package.
Key Timing Parameters/Part Numbers
Highest sustained bandwidth per DRAM device
- 2.1GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simultaneously at full bandwidth data rates
s
Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
s
Advanced power management:
- Multiple low power states allows flexibility in
power consumption versus time to transition to
active state
- Power-down self-refresh
s
Organization: 1Kbyte pages and 32 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
- x16 organization for low cost applications
s
711
45
128Ms-45-711-C
256Kx16x32s-C
s
Core Access
Time (ns)
256Kx16x32s-C
Features
I/O Freq.
MHz
800
45
128Ms-45-800-C
256Kx16x32s-C
800
42.5
128Ms-42.5-800-C
256Kx16x32s-C
1066
35
128Ms-35-1066-C
256Kx18x32s-C
711
45
144Ms-45-711-C
256Kx18x32s-C
800
45
144Ms-45-800-C
256Kx18x32s-C
800
42.5
144Ms-42.5-800-C
256Kx18x32s-C
1066
35
144Ms-35-1066-C
Organizationa
Part
Number
a. The “32s” designation indicates that this RDRAM core is
composed of 32 banks which use a “split” bank architecture.
Related Documentation
Data sheets for the Rambus memory system components are available on the Rambus website at
http://www.rambus.com. Please obtain the "Documentation Change History"for this data sheet. The
DCH is an integral part of the data sheet and contains
the most recent information about changes made to the
published version. Check the Rambus website regularly for the latest DCH and data sheet updates.
Uses Rambus Signaling Level (RSL) for up to
1066MHz operation
Document DL0091
Version 0.97
Preliminary Information
Page 1
