RDRAM® for Short Channel
256/288-Mbit (512Kx16/18x32s-C)
Preliminary Information
Overview
The RDRAM® is a general purpose high-performance
memory device suitable for use in a broad range of
applications including computer memory, graphics,
video, and any other application where high bandwidth and low latency are required.
The 256/288-Mbit RDRAM® devices are extremely
high-speed CMOS DRAMs organized as 16M words
by 16 or 18 bits. The use of Rambus Signaling Level
(RSL) technology permits 711MHz to 1066MHz
transfer rates while using conventional system and
board design technologies. RDRAM devices are
capable of sustained data transfers at 0.93 ns per two
bytes (7.5ns per sixteen bytes).
The architecture of the RDRAM devices allows the
highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The
separate control and data buses with independent row
and column control yield over 95% bus efficiency. The
device’s 32 banks support up to four simultaneous
transactions.
System-oriented features for mobile, graphics and
large memory systems include power management,
byte masking, and x18 organization. The two data bits
in the x18 organization are general and can be used for
additional storage and bandwidth or for error correction.
s
s
s
s
The 256/288-Mbit RDRAM devices are offered in a
CSP horizontal package suitable for desktop as well as
low-profile add-in card and mobile applications.
Key Timing Parameters/Part Numbers
Organizationa
I/O Freq. Core Access Time
MHz
(ns)
Part
Number
Highest sustained bandwidth per DRAM device
- 2.1GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simultaneously at full bandwidth data rates
Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
Advanced power management:
- Multiple low power states allows flexibility in
power consumption versus time to transition to
active state
- Power-down self-refresh
Organization: 2kbyte pages and 32 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
- x16 organization for low cost applications
512Kx16x32s-C
800
45
256Ms-45-800-C
512Kx16x32s-C
1066
40
256Ms-40-1066-C
512Kx18x32s-C
800
45
288Ms-45-800-C
512Kx18x32s-C
Features
s
Figure 1: Direct RDRAM CSP Package
1066
40
288Ms-40-1066-C
a. The bank designations are described in a later section. Refer to
Section "Row and Column Cycle Description" on page 17.
32s - 32 banks which use a “split” bank architecture
16d - 16 banks which use a “doubled” bank architecture
4i - 4 banks which use an “independent” bank architecture.
Related Documentation
Datasheets for the RDRAM memory system components are available on the Rambus website at
www.rdram.com. Please obtain the "Documentation
Change History"for this datasheet. The DCH is an
integral part of the data sheet and contains the most
recent information about changes made to the
published version. Check the RDRAM website regularly for the latest DCH and datasheet updates.
Uses RSL for up to 1066MHz operation
Document DL-0108-098
Version 0.98
Preliminary Information
Page 1
