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CoolRunner XPLA3 CPLD
DS012 (v2.5) May 26, 2009
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Product Specification
14
Features
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Fast Zero Power (FZP) design technique provides
ultra-low power and very high speed
- Typical Standby Current of 17 to 18 μA at 25°C
Innovative CoolRunner™ XPLA3 architecture
combines high speed with extreme flexibility
Based on industry's first TotalCMOS PLD — both
CMOS design and process technologies
Advanced 0.35μ five layer metal EEPROM process
- 1,000 erase/program cycles guaranteed
- 20 years data retention guaranteed
3V, In-System Programmable (ISP) using JTAG IEEE
1149.1 interface
- Full Boundary-Scan Test (IEEE 1149.1)
- Fast programming times
Support for complex asynchronous clocking
- 16 product term clocks and four local control term
clocks per function block
- Four global clocks and one universal control term
clock per device
Excellent pin retention during design changes
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Table 1: CoolRunner XPLA3 Device Family
XCR3032XL
XCR3064XL
Macrocells
Usable Gates
Registers
TPD (ns)
TSU (ns)
TCO (ns)
Fsystem (MHz)
ICCSB (μA)
32
750
32
4.5
3.0
3.5
213
17
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Available in commercial grade and extended voltage
(2.7V to 3.6V) industrial grade
5V tolerant I/O pins
Input register setup time of 2.5 ns
Single pass logic expandable to 48 product terms
High-speed pin-to-pin delays of 5.0 ns
Slew rate control per output
100% routable
Security bit prevents unauthorized access
Supports hot-plugging capability
Design entry/verification using Xilinx or industry
standard CAE tools
Innovative Control Term structure provides:
- Asynchronous macrocell clocking
- Asynchronous macrocell register preset/reset
- Clock enable control per macrocell
Four output enable controls per function block
Foldback NAND for synthesis optimization
Universal 3-state which facilitates "bed of nails" testing
Available in Chip-scale BGA, Fineline BGA, and QFP
packages. Pb-free available for most package types.
See Xilinx Packaging for more information.
XCR3128XL
XCR3256XL
XCR3384XL
XCR3512XL
128
3,000
128
5.5
3.5
4
175
17
256
6,000
256
7.0
4.3
4.5
154
18
384
9,000
384
7.0
4.3
4.5
135
18
512
12,000
512
7.0
3.8
5.0
135
18
64
1,500
64
5.5
3.5
4
192
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Table 2: CoolRunner XPLA3 Packages and User I/O Pins
XCR3032XL
44-pin VQFP
48-pin 0.8mm CSP
56-pin 0.5mm CSP
100-pin VQFP
144-pin 0.8mm CSP
144-pin TQFP
208-pin PQFP
256-pin Fineline BGA
280-pin 0.8mm CSP
324-pin Fineline BGA
1.
2.
3.
XCR3064XL
XCR3128XL
XCR3256XL
XCR3384XL
XCR3512XL
36
36
-
36
40
48
68
-
84
108
108
-
120
164
164
164
-
118(1)
172
212
220
180
212
260
XCR3384XL TQ144 JTAG pins are not compatible with other members of the CoolRunner XPLA3 family in the TQ144 package.
Most packages are available in Pb-Free option. See individual data sheets for more details.
The 44-pin PLCC package is discontinued per XCN07022.
© 2000–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS012 (v2.5) May 26, 2009
Product Specification
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