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74HCT165
74HC165; 74HCT165 8-bit parallel-in/serial out shift register Rev. 4 — 28 December 2015 Product data sheet 1. General description The 74HC165; 74HCT165 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH on CE will disable the CP input. Inputs include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits Asynchronous 8-bit parallel load Synchronous serial input Complies with JEDEC standard no. 7A Input levels: For 74HC165: CMOS level For 74HCT165: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from 40 C to +85 C and from 40 C to +125 C 3. Applications Parallel-to-serial data conversion 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74HC165D Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm 74HCT165D 74HC165DB 74HCT165DB SOT338-1
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