OP4005B1
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Quartz SAW Stabilized Differential Output Technology
Very Low Jitter Fundamental-Mode Operation at 622.08 MHz
Voltage Tunable for Phase Locked Loop Applications
Timing Reference for Optical Data Communications Systems
The OP4005B1 is a voltage-controlled SAW clock (VCSC) designed for phase-locked loop (PLL) applications
in optical data communications systems. The differential outputs of the OP4005B1 are generated by high-Q,
fundamental mode quartz surface acoustic wave (SAW) technology. This technique provides very low output
jitter and phase noise, plus excellent immunity to power supply noise. The OP4005B1 differential outputs
feature ±1% symmetry, and can be DC-configured to drive a wide range of high-speed logic families. The
OP4005B1 is packaged in a hermetic metal-ceramic LCC.
Absolute Maximum Ratings
Rating
Value
622.08 MHz
Optical
Timing Clock
Units
DC Suppy Voltage
0 to 5.5
Vdc
Tune Voltage
0 to 5.5
Vdc
-55 to 100
°C
Case Temperature
SMC-08A
Electrical Characteristics
Characteristic
Operating Frequency
Sym
Absolute Frequency
Notes
fO
1
622.08
2
±100
Tuning Range
Tuning Voltage
1
Tuning Linearity
Voltage into 50 Ω (VSWR ≤ 1.2)
Operating Load VSWR
Typical
Maximum
ppm
Vdc
±5
%
kHz
200
VO
1,3
0.60
1.1
45
2:1
55
%
-15
dBc
1,3
Symmetry
3, 4, 5
3, 4, 6
Harmonic Spurious
3, 4, 6, 7
Nonharmonic Spurious
Units
MHz
3.3
0
1
Modulation Bandwidth
Q and Q Output
Minimum
VP-P
dBc
-60
3, 6
-70
dBc/Hz
3, 6
-100
dBc/Hz
@ 10 kHz offset
3, 6
-125
dBc/Hz
Noise Floor
3, 6
-150
dBc/Hz
RMS Jitter (10kHz to 80MHz)
3, 4, 6, 7
0.1
ps
No Noise on VCC
Q and Q Jitter
@ 100 Hz offset
@ 1 kHz offset
Phase Noise
3, 4, 6, 7
12
psP-P
12
psP-P
200 mVP-P Noise, from 1 MHz to ½ fO on VCC
Input Impedence (Tuning Port)
Output DC Resistance (between Q & Q)
DC Power Supply
Operating Voltage
Operating Current
Operating Case Temperature
Lid Symbolization (YY=Year, WW=Week)
3
8
1, 3
1, 3
3.13
ICC
1, 3
1, 3
KΩ
KΩ
50
VCC
10
-40°C
TC
3.3 or 5.0
5.25
70
Vdc
+85°C
°C
mA
RFM OP4005B1 YYWW
CAUTION: Electrostatic Sensitive Device. Observe precautions for handling. COCOM CAUTION: Approval by the U.S.
Department of Commerce is required prior to export of this device.
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Unless otherwise noted, all specifications include the combined effects of load VSWR, VCC and TC.
Net tuning range after tuning out the effects of initial manufacturing tolerances, VSWR pushing/pulling, VCC, TC and aging.
The internal design, manufacturing processes, and specifications of this device are subject to change without notice.
Specified only for a balanced load with a VSWR < 1.2 ( 50 ohms each side), and a VCC = 3.0 Vdc.
Symmetry is defined as the width in (% of total period) measure at 50% of the peak-to-peak voltage of either output.
Jitter and other noise outputs due to power supply noise or mechanical vibration are not included in this specification except where noted.
Applies to period jitter of either differential output. Measured with a Tektronix CSA803 signal analyzer with at least 1000 samples.
One or more of the following United States patents apply: 4, 616,197; 4,670,681; 4,760,352.
www.RFM.com
E-mail: info@rfm.com
©2008 by RF Monolithics, Inc.
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OP4005B1 - 3/27/08
