GAL20V8
High Performance E2CMOS PLD
Generic Array Logic™
Features
Functional Block Diagram
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— 5 ns Maximum Propagation Delay
— Fmax = 166 MHz
— 4 ns Maximum from Clock Input to Data Output
— UltraMOS® Advanced CMOS Technology
I/CLK
I
IMUX
I
CLK
8
OLMC
8
OLMC
8
OLMC
8
OLMC
8
I/O/Q
OLMC
8
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
— 75mA Typ Icc on Low Power Device
— 45mA Typ Icc on Quarter Power Device
OLMC
I
• ACTIVE PULL-UPS ON ALL PINS
I/O/Q
PROGRAMMABLE
AND-ARRAY
(64 X 40)
I
2
• E CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
I
I
• EIGHT OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
— Programmable Output Polarity
— Also Emulates 24-pin PAL® Devices with Full Function/
Fuse Map/Parametric Compatibility
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability
8 OLMC
I/O/Q
8
I/O/Q
I
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
I
OLMC
OE
I
I
IMUX
I/OE
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
Description
Pin Configuration
DIP
The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed
performance available in the PLD market. High speed erase times
(<100ms) allow the devices to be reprogrammed quickly and efficiently.
PLCC
4
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. An important subset of the many architecture configurations possible with the GAL20V8 are the PAL architectures listed
in the table of the macrocell description section. GAL20V8 devices
are capable of emulating any of these PAL architectures with full
function/fuse map/parametric compatibility.
I
2
28
7
23
GAL20V8
NC
I
9
Top View
21
11
I
NC
I/O/Q
19
18
16
I/OE
14
I
I
12
GAL
20V8
I
I
I/O/Q
I
I/O/Q
I/O/Q
I/O/Q
6
I
I/O/Q
I
I/O/Q
I
I/O/Q
I
I/O/Q
I/O/Q
GND
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
I/O/Q
I/O/Q
NC
I
I
Vcc
I
I/O/Q
I
I
24
I
26
25
5
1
I
I/O/Q
I
Vcc
I/CLK
NC
I
I
I/CLK
18
I/O/Q
I/O/Q
I
I
GND
12
13
I/OE
Copyright © 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
20v8_05
1
November 2003
