87
CY7C187
64K x 1 Static RAM
Features
vided by an active LOW Chip Enable (CE) and three-state drivers. The CY7C187 has an automatic power-down feature,
reducing the power consumption by 56% when deselected.
• High speed
— 15 ns
• CMOS for optimum speed/power
• Low active power
— 495 mW
• Low standby power
— 220 mW
• TTL compatible inputs and outputs
• Automatic power-down when deselected
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW. Data on the
input pin (DIN) is written into the memory location specified on
the address pins (A0 through A15).
Reading the device is accomplished by taking the Chip Enable
(CE) LOW, while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location specified on the address pin will appear on the data output (DOUT)
pin.
The output pin stays in high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW.
Functional Description
The CY7C187 utilizes a die coat to insure alpha immunity.
The CY7C187 is a high-performance CMOS static RAM organized as 65,536 words x 1 bit. Easy memory expansion is pro-
Logic Block Diagram
Pin Configurations
SOJ
Top View
DI
A0
A1
A2
A3
A4
A5
NC
A6
A7
SENSE AMPS
A12
A13
A14
A15
A0
A1
A2
A3
ROW DECODER
INPUT BUFFER
256 x 256
ARRAY
DO
DOUT
WE
GND
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
DIP
Top View
VCC
A15
A14
A13
A12
NC
A11
A10
A9
A8
DIN
CE
A0
A1
A2
A3
A4
A5
A6
A7
DOUT
WE
GND
C187–3
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
VCC
A15
A14
A13
A12
A11
A10
A9
A8
DIN
CE
C187–2
CE
COLUMN DECODER
POWER
DOWN
A4
A5
A6
A7
A8
A9
A10
A11
WE
C187–1
Selection Guide[1]
7C187-15
7C187-20
7C187-25
7C187-35
Maximum Access Time (ns)
15
20
25
35
Maximum Operating Current (mA)
90
80
70
70
40/20
40/20
20/20
20/20
Maximum Standby Current (mA)
Note:
1. For military specifications, see the CY7C187A datasheet.
Cypress Semiconductor Corporation
Document #: 38-05044 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 24, 2001