MC10ELT24, MC100ELT24
5V TTL to Differential
ECL Translator
Description
http://onsemi.com
MARKING DIAGRAMS*
8
8
Features
•
•
•
•
•
0.8 ns tPHL, 0.95 ns tPLH Typical Propagation Delay
PNP TTL Inputs for Minimal Loading
Flow Through Pinouts
Operating Range: VCC = 4.5 V to 5.5 V; VEE = −4.2 V to −5.5 V with
GND = 0 V
Pb−Free Packages are Available
1
SOIC−8
D SUFFIX
CASE 751
1
8
HLT24
ALYW
G
8
8
1
1
1
8
HT24
ALYWG
G
1
KT24
ALYWG
G
5E MG
G
TSSOP−8
DT SUFFIX
CASE 948R
KLT24
ALYW
G
DFN8
MN SUFFIX
CASE 506AA
H
K
5E
2T
M
= MC10
= MC100
= MC10
= MC100
= Date Code
2T MG
G
The MC10ELT/100ELT24 is a TTL to differential ECL translator.
Because ECL levels are used a +5 V, −5.2 V (or −4.5 V) and ground
are required. The small outline 8−lead package and the single gate of
the ELT24 makes it ideal for those applications where space,
performance and low power are at a premium.
The 100 Series contains temperature compensation.
1
4
1
4
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 10
1
Publication Order Number:
MC10ELT24/D
