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MEB12C-5
TS68C000 Low Power HCMOS 16-/32-bit Hi-Rel Microprocessor Datasheet Features • • • • • • • • • 16-/32-bit Data and Address Register 16-Mbyte Direct Addressing Range 56 Powerful Instruction Types Operations on Five Main Data Types Memory Mapped Input/Output 14 Addressing Modes Three Available Versions: 8 MHz/10 MHz and 12.5 MHz Military Temperature Range: -55/+125°C Power Supply: 5VDC ± 10% Description The TS68C000 reduced power consumption device dissipates an order of magnitude less power than the HMOS TS68000. The TS68C000 is an implementation of the TS68000 16/32 microprocessor architecture. The TS68C000 has a 16-bit data bus and 24-bit address bus while the full architecture provides for 32-bit address and data-buses. It is completely codecompatible with the HMOS TS68000, TS68008 8-bit data bus implementation of the TS68000 and the TS68020 32-bit implementation of the architecture. Any user-mode programs written using the TS68C000 instruction set will run unchanged on the TS68000, TS68008 and TS68020. This is possible because the user programming model is identical for all processors and the instruction sets are proper sub-sets of the complete architecture. Screening/Quality This product is manufactured in full compliance with: • MIL-STD-883 class B • DESC drawing 5962-89462 • e2v standards C Suffix DIL 64 Ceramic Package E Suffix LCCC 68 Leadless Ceramic Chip Carrier F Suffix CQFP 68 Ceramic Quad Flat Pack (on reque R Suffix PGA 68 Pin Grid Array Visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors SAS 2007 0853B–HIREL–09/07
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