512Mb: x4, x8, x16 DDR SDRAM
Features
Double Data Rate (DDR) SDRAM
MT46V128M4 – 32 Meg x 4 x 4 banks
MT46V64M8 – 16 Meg x 8 x 4 banks
MT46V32M16 – 8 Meg x 16 x 4 banks
For the latest data sheet, refer to Micron’s Web site: www.micron.com/ddrsdram
Features
Options
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR400)
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two
– one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto refresh and self refresh modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
• tRAS lockout supported (tRAP = tRCD)
Table 1:
128M4
64M8
32M16
TG
P
FN
BN
-5B
-6
-6T
-75E
-75Z
-75
None
L
None
IT
:C
:D
:F
Addressing Configuration
128 Meg x 4
32 Meg x 4 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
4K (A0-A9, A11, A12)
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
Table 2:
Marking
• Configuration
128 Meg x 4 (32 Meg x 4 x 4 banks)
64 Meg x 8 (16 Meg x 8 x 4 banks)
32 Meg x 16 (8 Meg x 16 x 4 banks)
• Plastic Package
66-pin TSOP
66-pin TSOP Lead-free
60-Ball FBGA (10 x 12.5mm)
60-Ball FBGA (10 x 12.5mm) Lead-free
• Timing – cycle time
5ns @ CL = 3 (DDR400B)
6ns @ CL = 2.5 (DDR333) (FBGA only)
6ns @ CL = 2.5 (DDR333) (TSOP only)
7.5ns @ CL = 2 (DDR266)
7.5ns @ CL = 2 (DDR266A)
7.5ns @ CL = 2.5 (DDR266B)
• Self refresh
Standard
Low-Power self refresh
• Temperature rating
Standard (0°C to +70°C)
Industrial (-40°C to +85°C)
• Revision
x4, x8, x16
x4, x8
x4, x8, x16
64 Meg x 8
16 Meg x 8 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
2K (A0–A9, A11)
32 Meg x 16
8 Meg x 16 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
1K (A0–A9)
Key Timing Parameters
CL = CAS (Read) latency; data-out window is MIN clock rate with 50% duty cycle @ CL = 2, CL = 2.5, or CL = 3
Speed
Grade
-5B
-6
6T
-75E/-75Z
-75
Clock Rate
CL = 2
133 MHz
133 MHz
133 MHz
133 MHz
100 MHz
09005aef80a1d9e7
512MBDDRx4x8x16_1.fm - Rev. J 1/06 EN
CL = 2.5
167 MHz
167 MHz
167 MHz
133 MHz
133 MHz
CL = 3
200 MHz
NA
NA
NA
NA
1
Data-Out Window
1.6ns
2.1ns
2.0ns
2.5ns
2.5ns
Access
Window
±0.70ns
±0.70ns
±0.70ns
±0.75ns
±0.75ns
DQS–DQ
Skew
+0.40ns
+0.40ns
+0.45ns
+0.50ns
+0.50ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000–2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
