Zynq-7000 All Programmable SoC Data Sheet:
Overview
DS190 (v1.11) June 7, 2017
Product Specification
Zynq-7000 All Programmable SoC First Generation Architecture
The Zynq®-7000 family is based on the Xilinx All Programmable SoC architecture. These products integrate a feature-rich dual-core or
single-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM
Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral
connectivity interfaces.
Processing System (PS)
ARM Cortex-A9 Based
Application Processor Unit (APU)
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I/O Peripherals and Interfaces
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Jazelle® RCT execution Environment Architecture
NEON™ media-processing engine
Single and double precision Vector Floating Point Unit (VFPU)
CoreSight™ and Program Trace Macrocell (PTM)
Timer and Interrupts
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Three watchdog timers
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One global timer
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Two triple-timer counters
Caches
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32 KB Level 1 4-way set-associative instruction and data caches
(independent for each CPU)
512 KB 8-way set-associative Level 2 cache
(shared between the CPUs)
Byte-parity support
Two full CAN 2.0B compliant CAN bus interfaces
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CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard
compliant
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External PHY interface
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Two SD/SDIO 2.0/MMC3.31 compliant controllers
Two full-duplex SPI ports with three peripheral chip selects
Two high-speed UARTs (up to 1 Mb/s)
Two master and slave I2C interfaces
GPIO with four 32-bit banks, of which up to 54 bits can be used with
the PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits
(up to two banks of 32b) connected to the Programmable Logic
Up to 54 flexible multiplexed I/O (MIO) for peripheral pin assignments
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On-Chip Memory
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Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints
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USB 2.0 compliant device IP core
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Supports on-the-go, high-speed, full-speed, and low-speed
modes
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Intel EHCI compliant USB host
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8-bit ULPI external PHY interface
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2.5 DMIPS/MHz per CPU
CPU frequency: Up to 1 GHz
Coherent multiprocessor support
ARMv7-A architecture
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TrustZone® security
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Thumb®-2 instruction set
Two 10/100/1000 tri-speed Ethernet MAC peripherals with
IEEE Std 802.3 and IEEE Std 1588 revision 2.0 support
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Scatter-gather DMA capability
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Recognition of 1588 rev. 2 PTP frames
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GMII, RGMII, and SGMII interfaces
Interconnect
On-chip boot ROM
256 KB on-chip RAM (OCM)
Byte-parity support
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External Memory Interfaces
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Multiprotocol dynamic memory controller
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High-bandwidth connectivity within PS and between PS and PL
ARM AMBA® AXI based
QoS support on critical masters for latency and bandwidth control
16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2
memories
ECC support in 16-bit mode
1GB of address space using single rank of 8-, 16-, or 32-bit-wide
memories
Static memory interfaces
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8-bit SRAM data bus with up to 64 MB support
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Parallel NOR flash support
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ONFI1.0 NAND flash support (1-bit ECC)
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1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit)
serial NOR flash
8-Channel DMA Controller
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Memory-to-memory, memory-to-peripheral, peripheral-to-memory,
and scatter-gather transaction support
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in the United States and other countries. AMBA, AMBA Designer, ARM, ARM Cortex-A9, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and other countries.
PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS190 (v1.11) June 7, 2017
Product Specification
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