FDS6982S
Dual Notebook Power Supply N-Channel PowerTrench SyncFet™
General Description
Features
The FDS6982S is designed to replace two single SO-8
MOSFETs and Schottky diode in synchronous DC:DC
power supplies that provide various peripheral voltages
for notebook computers and other battery powered
electronic devices. FDS6982S contains two unique
30V, N-channel, logic level, PowerTrench MOSFETs
designed to maximize power conversion efficiency.
•
Q2:
Optimized to minimize conduction losses
Includes SyncFET Schottky body diode
RDS(on) = 0.016Ω=@ VGS = 10V
8.6A, 30V
RDS(on) = 0.022Ω=@ VGS = 4.5V
•
The high-side switch (Q1) is designed with specific
emphasis on reducing switching losses while the lowside switch (Q2) is optimized to reduce conduction
losses. Q2 also includes an integrated Schottky diode
using Fairchild’s monolithic SyncFET technology.
Q1:
Optimized for low switching losses
Low Gate Charge ( 8.5 nC typical)
RDS(on) = 0.028Ω=@ VGS = 10V
6.3A, 30V
RDS(on) = 0.035Ω=@ VGS = 4.5V
D1
5
D1
D2
4
6
D2
3
Q1
7
SO-8
S2
G2
S1
G1
Absolute Maximum Ratings
Symbol
8
Q2
Drain Current
- Continuous
- Pulsed
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
PD
(Note 1a)
Units
30
±20
8.6
30
±20
6.3
20
V
V
A
2
1.6
1
0.9
-55 to +150
°C
(Note 1a)
78
°C/W
(Note 1)
40
°C/W
(Note 1a)
(Note 1b)
(Note 1c)
TJ, TSTG
Q1
30
Drain-Source Voltage
Gate-Source Voltage
ID
1
TA = 25°C unless otherwise noted
Parameter
VDSS
VGSS
2
Q2
Operating and Storage Junction Temperature Range
W
Thermal Characteristics
RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
FDS6982S
FDS6982S
13”
12mm
2500 units
2000 Fairchild Semiconductor Corporation
FDS6982S Rev C(W)
FDS6982S
September 2000
Electrical Characteristics
Symbol
(continued)
Parameter
Switching Characteristics
td(on)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Type Min
Typ
Max Units
(Note 2)
Turn-On Rise Time
td(off)
Test Conditions
Turn-On Delay Time
tr
TA = 25°C unless otherwise noted
Gate-Drain Charge
VDD = 15 V, ID = 1 A,
VGS = 10V, RGEN = 6 Ω
Q2
VDS = 15 V, ID = 11.5 A, VGS = 5 V
Q1
VDS = 15 V, ID = 6.3 A, VGS = 5 V
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
10
10
10
14
34
21
14
7
17.5
8.5
6.3
2.4
5.4
3.1
18
18
18
25
55
34
23
14
25
12
ns
ns
ns
ns
nC
nC
nC
Drain–Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
tRR
Reverse Recovery Time
QRR
VSD
IF = 11.5A,
diF/dt = 300 A/µs
Reverse Recovery Charge
Drain-Source Diode Forward VGS = 0 V, IS = 3 A
VGS = 0 V, IS = 6 A
Voltage
VGS = 0 V, IS = 1.3 A
Q2
Q1
Q2
20
ns
Q2
Q2
Q1
19.7
0.42
0.56
0.70
nC
V
(Note 3)
(Note 2)
(Note 2)
(Note 2)
3.0
1.3
.7
A
1.2
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 78°/W when
mounted on a
0.5 in2 pad of 2 oz
copper
b) 125°/W when
mounted on a .02 in2
pad of 2 oz copper
c) 135°/W when mounted on a
minimum pad.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
3. See “SyncFET Schottky body diode characteristics” below.
FDS6982S Rev C (W)
