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CY7C342B
128-Macrocell MAX® EPLD
Features
100% user-configurable, allowing the device to accommodate
a variety of independent logic functions.
• 128 macrocells in eight logic array blocks (LABs)
The 128 macrocells in the CY7C342B are divided into eight
LABs, 16 per LAB. There are 256 expander product terms, 32
per LAB, to be used and shared by the macrocells within each
LAB.
• Eight dedicated inputs, 52 bidirectional I/O pins
• Programmable interconnect array
• Advanced 0.65-micron CMOS technology to increase
performance
Each LAB is interconnected with a programmable interconnect
array, allowing all signals to be routed throughout the chip.
• Available in 68-pin HLCC, PLCC, and PGA packages
Functional Description
The CY7C342B is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX® architecture is
The speed and density of the CY7C342B allows it to be used in a
wide range of applications, from replacement of large amounts of
7400-series TTL logic, to complex controllers and multifunction
chips. With greater than 25 times the functionality of 20-pin PLDs,
the CY7C342B allows the replacement of over 50 TTL devices.
By replacing large amounts of logic, the CY7C342B reduces board
space, part count, and increases system reliability.
Logic Block Diagram
1 (B6)
INPUT/CLK
INPUT
(A7)
2 (A6)
INPUT
INPUT
(A8)
66
32 (L4)
INPUT
INPUT
(L6)
36
34 (L5)
INPUT
INPUT
(K6)
35
68
SYSTEM CLOCK
4 (A5)
5 (B4)
6 (A4)
7 (B3)
8 (A3)
9 (A2)
10 (B2)
11 (B1)
12 (C2)
13 (C1)
14 (D2)
15 (D1)
17 (E1)
LAB A
MACROCELL 1
MACROCELL 2
MACROCELL 3
MACROCELL 4
MACROCELL 5
MACROCELL 6
MACROCELL 7
MACROCELL 8
MACROCELL 9–16
LAB H
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
MACROCELL 121–128
LAB B
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
LAB G
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
MACROCELL 22–32
18 (F2)
19 (F1)
21 (G1)
22 (H2)
23 (H1)
(D11) 57
(D10) 56
(E11) 55
(F11) 53
(F10) 52
MACROCELL 102–112
P
I
A
LAB C
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 37
LAB F
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 38–48
24 (J2)
25 (J1)
26 (K1)
27 (K2)
28 (L2)
29 (K3)
30 (L3)
31 (K4)
(B8) 65
(A9) 64
(B9) 63
(A10) 62
(B10) 61
(B11) 60
(C11) 59
(C10) 58
MACROCELL 86–96
LAB D
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
MACROCELL 53
MACROCELL 54
MACROCELL 55
MACROCELL 56
LAB E
MACROCELL 72
MACROCELL 71
MACROCELL 70
MACROCELL 69
MACROCELL 68
MACROCELL 67
MACROCELL 66
MACROCELL 65
(G11) 51
(H11) 49
(H10) 48
(J11) 47
(J10) 46
(K11) 45
(K10) 44
(L10) 43
(L9) 42
(K9) 41
(L8) 40
(K8) 39
(L7) 38
MACROCELL 73–80
MACROCELL 57–64
3, 20, 37, 54 (B5, G2, K7, E10)
VCC
16, 33, 50, 67 (E2, K5, G10, B7)
() – PERTAIN TO 68-PIN PGA PACKAGE
GND
Cypress Semiconductor Corporation
Document #: 38-03014 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 22, 2004
