14-Bit, 150 MSPS, 1.8 V
Analog-to-Digital Converter
AD9254
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
AD9254
VIN+
VIN–
Macro, micro, and pico cell infrastructure
GENERAL DESCRIPTION
The AD9254 is a monolithic, single 1.8 V supply, 14-bit, 150 MSPS
analog-to-digital converter (ADC), featuring a high performance
sample-and-hold amplifier (SHA) and on-chip voltage reference.
The product uses a multistage differential pipeline architecture
with output error correction logic to provide 14-bit accuracy at
150 MSPS data rates and guarantees no missing codes over the
full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets, including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9254 is suitable for applications in communications,
imaging, and medical ultrasound.
A differential clock input controls all internal conversion cycles.
A duty cycle stabilizer (DCS) compensates for wide variations in
the clock duty cycle while maintaining excellent overall ADC
performance.
8-STAGE
1 1/2-BIT PIPELINE
MDAC1
SHA
4
8
A/D
3
A/D
REFT
REFB
CORRECTION LOGIC
OR
15
OUTPUT BUFFERS
DCO
D13 (MSB)
VREF
D0 (LSB)
SENSE
0.5V
REF
SELECT
AGND
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
CDMA2000, WCDMA, TD-SCDMA, and WiMax
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
DRVDD
CLOCK
DUTY CYCLE
STABILIZER
CLK+
CLK–
SCLK/DFS
MODE
SELECT
PDWN
SDIO/DCS
CSB
DRGND
06216-001
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR = 71.8 dBc (72.8 dBFS) to 70 MHz input
SFDR = 84 dBc to 70 MHz input
Low power: 430 mW @ 150 MSPS
Differential input with 650 MHz bandwidth
On-chip voltage reference and sample-and-hold amplifier
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary, Gray code, or twos complement data format
Clock duty cycle stabilizer
Data output clock
Serial port control
Built-in selectable digital test pattern generation
Programmable clock and data alignment
Figure 1.
The digital output data is presented in offset binary, Gray code, or
twos complement formats. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic.
The AD9254 is available in a 48-lead LFCSP_VQ and is specified
over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1.
The AD9254 operates from a single 1.8 V power supply
and features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
2.
The patented SHA input maintains excellent performance
for input frequencies up to 225 MHz.
3.
The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
4.
A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or Gray coding), enabling the
clock DCS, power-down, and voltage reference mode.
5.
The AD9254 is pin-compatible with the AD9233, allowing
a simple migration from 12 bits to 14 bits.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
