NXP family of ULPI
Hi-Speed USB transceivers
ISP150x, ISP170x
Best-in-class ULPI transceivers for
mobile and portable applications
Designed for use with ASICs, FPGAs, and system chipsets that interface with the physical layer
of the USB connection, these first- and second-generation transceivers provide reliable USB
performance in a low-pin format and support a full range of portable applications,
including mobile phones.
Key features
Ñ Fully compliant with:
- Universal Serial Bus Specification Revision 2.0
- On-The-Go Supplement to the USB Specification
Revision 1.2
- UTMI+ Low Pin Interface (ULPI) Specification Revision 1.1
Ñ High-speed (480 Mbps), full-speed (12 Mbps) and low-speed
(1.5 Mbps) data rates
Ñ Interfaces to Hi-Speed USB host, peripheral, and dual-role
device cores
Ñ Highly optimized ULPI-compliant interface
- 60-MHz, 4- or 8-bit interface between ASIC and transceiver
- Integrated PLL supports 60-MHz input clock and a wide
spectrum of crystal or clock frequencies.
- Fully programmable ULPI-compliant register set
- Internal power-on reset circuit
Ñ Integrated resistors: 45-Ω high-speed terminations, 1.5-kΩ
full-speed device pull-up, and 15-kΩ host terminations
Ñ Guaranteed VBUS impedance of 80 to 100 kΩ for
ISP1702, ISP1703
Ñ Support for bus reset, suspend, resume, and high-speed
detection handshake (chirp)
Ñ Low suspend current (50 µA) and low power-down mode
current (0.5 µA)
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Input power supply: 3.0 to 4.5 V
Charger detection
ULPI SDR and DDR modes available
UART pass-through mode
Space-saving packages (HVQFN32/24, TFBGA36, WLCSP25)
NXP offers two generations of UTMI+ Low Pin Interface (ULPI)
Hi-Speed USB transceivers. Both generations build on
the proven, fully compliant NXP architecture for ULPI, which
allows USB ASICs, FPGAs, and system chipsets to interface
with the physical layer of the USB connection. All offer very
small form factor and very low power.
The core architecture supports high-speed (480 Mbps),
full-speed (12 Mbps), and low-speed (1.5 Mbps) data rates,
and includes a highly optimized interface that operates at
60 MHz and uses only eight (DDR) or twelve (SDR) signals
between the ASIC and the transceiver.
An integrated phase-locked loop (PLL) supports a 60-MHz
input clock and a range of crystal or clock frequencies.
The architecture also includes a fully programmable,
