Product Obsolete or Under Obsolescence
<
B
L
R
DS027 (v3.5) June 25, 2008
XC1700E, XC1700EL, and XC1700L
Series Configuration PROMs
Product Specification
8
Features
•
•
XC1700E series are available in 5V and 3.3V versions
•
One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx®
FPGAs
XC1700L series are available in 3.3V only
•
Available in compact plastic packages: 8-pin SOIC, 8pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44pin PLCC or 44-pin VQFP
•
Simple interface to the FPGA; requires only one user
I/O pin
•
Cascadable for storing longer or multiple bitstreams
•
•
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
Programming support by leading programmer
manufacturers
•
•
XC17128E/EL, XC17256E/EL, XC1701, and XC1700L
series support fast configuration
Design support using the Xilinx Alliance and
Foundation™ software packages
•
•
Guaranteed 20 year life data retention
Low-power CMOS floating-gate process
•
Lead-free (Pb-free) packaging available
Description
The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams. See Figure 1 for a
simplified block diagram.
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. After configured, it disables the
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or
Foundation software compiles the FPGA design file into a
standard Hex format, which is then transferred to most
commercial PROM programmers.
X-Ref Target - Figure 1
VCC
RESET/
OE
or
OE/
RESET
VPP
GND
CEO
CE
CLK
Address Counter
EPROM
Cell
Matrix
TC
Output
OE
DATA
DS027_01_021500
Figure 1: Simplified Block Diagram (Does Not Show Programming Circuit)
© Copyright 1998-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS027 (v3.5) June 25, 2008
Product Specification
www.xilinx.com
1
