MC100LVEL34
3.3V ECL ÷2, ÷4, ÷8 Clock
Generation Chip
Description
The MC100LVEL34 is a low skew ÷ 2, ÷ 4, ÷ 8 clock generation
chip designed explicitly for low skew clock generation applications.
The internal dividers are synchronous to each other, therefore, the
common output edges are all precisely aligned. The VBB pin, an
internally generated voltage supply, is available to this device only.
For single−ended input conditions, the unused differential input is
connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, VBB should be left open.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the falling edge of
the input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon start−up, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple LVEL34s in a system.
Features
•
•
•
•
•
•
50 ps Typical Output-to-Output Skew
http://onsemi.com
MARKING
DIAGRAMS*
16
16
1
SO−16
D SUFFIX
CASE 751B
100LVEL34G
AWLYWW
1
16
16
1
TSSOP−16
DT SUFFIX
CASE 948F
100
VL34
ALYW G
G
1
A
= Assembly Location
L, WL = Wafer Lot
Y
= Year
W, WW = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Synchronous Enable/Disable
Master Reset for Synchronization
1.5 GHz Toggle Frequency
ORDERING INFORMATION
The 100 Series Contains Temperature Compensation.
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
PECL Mode Operating Range:
VCC = 3.0 V to 3.8 V with VEE = 0 V
• NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −3.8 V
Open Input Default State
•
• LVDS Input Compatible
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2014
April, 2014 − Rev. 4
1
Publication Order Number:
MC100LVEL34/D
