IDT5V991A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5V991A
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK™
FEATURES:
DESCRIPTION:
•
•
•
•
The IDT5V991A is a high fanout 3.3V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5V991A has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals that
may be hard-wired to appropriate HIGH-MID-LOW levels.
When the GND/sOE pin is held low, all the outputs are synchronously
enabled. However, if GND/sOE is held high, all the outputs except 3Q0 and
3Q1 are synchronously disabled.
Furthermore, when the VCCQ/PE is held high, all the outputs are
synchronized with the positive edge of the REF clock input. When VCCQ/
PE is held low, all the outputs are synchronized with the negative edge of
REF. Both devices have LVTTL outputs with 12mA balanced drive outputs.
REF is 5V tolerant
4 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 3.75MHz to 85MHz
2x, 4x, 1/2, and 1/4 outputs
3 skew grades:
IDT5V991A-2: tSKEW0<250ps
IDT5V991A-5: tSKEW0<500ps
IDT5V991A-7: tSKEW0<750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <200ps peak-to-peak
Available in 32-pin PLCC Package
•
•
•
•
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
GND/sOE
1Q0
Skew
Select
1Q1
3
3
1F1:0
VCCQ/PE
2Q0
Skew
Select
2Q1
3
3
REF
PLL
2F1:0
FB
3
FS
3Q0
Skew
Select
3Q1
3
3
3F1:0
4Q0
Skew
Select
4Q1
3
3
4F1:0
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SEPTEMBER 2001
1
c
2001
Integrated Device Technology, Inc.
DSC 5963/3
