64Mb: x32 SDRAM
Features
Synchronous DRAM
MT48LC2M32B2 – 512K x 32 x 4 banks
For the latest data sheet, refer to Micron’s Web site: www.micron.com/sdram
Features
Table 1:
• PC100 functionality
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge,
and auto refresh modes
• Self refresh mode
• 64ms, 4,096-cycle refresh (15.6µs/row)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• Supports CAS latency of 1, 2, and 3
Options
2 Meg x 32
512K x 32 x 4 banks
4K
2K (A0–A10)
4 (BA0, BA1)
256 (A0–A7)
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
Table 2:
Key Timing Parameters
CL = CAS (READ) latency
Speed
Grade
2M32B2
TG
P
B5
Clock
Frequency
-5
-55
-6
-7
Marking
• Configuration
2 Meg x 32 (512K x 32 x 4 banks)
• Plastic package - OCPL1
86-pin TSOP (400 mil)
86-pin TSOP (400 mil) lead-free
90-ball VFBGA (8mm x 13mm) lead-free
• Timing (cycle time)
5ns (200 MHz)
5.5ns (183 MHz)
6ns (166 MHz)
7ns (143 MHz)
• Die rev
• Operating temperature range
Commercial (0° to +70°C)
Extended (–40°C to +85°C)
Notes: 1. Off-center parting line.
2. Available on -6 and -7.
Address Table
200 MHz
183 MHz
166 MHz
143 MHz
Table 3:
CL = 3
Setup
Time
Hold
Time
4.5ns
5ns
5.5ns
5.5ns
1.5ns
1.5ns
1.5ns
2ns
1ns
1ns
1ns
1ns
64Mb (x32) SDRAM Part Number
Part Number
-5
-55
-6
-7
:G
Access
Time
MT48LC2M32B2TG
MT48LC2M32B2P
MT48LC2M32B2B5
Architecture
2 Meg x 32
2 Meg x 32
2 Meg x 32
None
IT2
Part Number Example:
MT48LC2M32B2P-7:G
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_1.fm - Rev. J 2/06 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
