LTC2207/LTC2206
16-Bit, 105Msps/80Msps
ADCs
DESCRIPTION
FEATURES
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Sample Rate: 105Msps/80Msps
78.2dBFS Noise Floor
100dB SFDR
SFDR >82dB at 250MHz (1.5VP-P Input Range)
PGA Front End (2.25VP-P or 1.5VP-P Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
Single 3.3V Supply
Power Dissipation: 900mW/725mW
Optional Clock Duty Cycle Stabilizer
Out-of-Range Indicator
Pin-Compatible Family
105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)
80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)
65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit)
40Msps: LTC2204 (16-Bit)
25Msps: LTC2203 (16-Bit) Single-Ended Clock
10Msps: LTC2202 (16-Bit) Single-Ended Clock
48-Pin 7mm × 7mm QFN Package
APPLICATIONS
■
■
■
■
■
■
The LTC®2207/LTC2206 are 105Msps/80Msps, sampling
16-bit A/D converters designed for digitizing high frequency, wide dynamic range signals up to input frequencies
of 700MHz. The input range of the ADC can be optimized
with the PGA front end.
The LTC2207/LTC2206 are perfect for demanding communications applications, with AC performance that
includes 78.2dB Noise Floor and 100dB spurious free
dynamic range (SFDR). Ultralow jitter of 80fsRMS allows
undersampling of high input frequencies with excellent
noise performance. Maximum DC specs include ±4LSB
INL, ±1LSB DNL (no missing codes) over temperature.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC+ and ENC– inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of
clock duty cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
TYPICAL APPLICATION
LTC2207: 64K Point FFT,
fIN = 14.8MHz, –1dBFS,
PGA = 0, 105Msps
3.3V
SENSE
OVDD
2.2μF
AIN+
1.25V
COMMON MODE
BIAS VOLTAGE
+
ANALOG
INPUT
AIN–
INTERNAL ADC
REFERENCE
GENERATOR
16-BIT
PIPELINED
ADC CORE
S/H
AMP
–
0.5V TO 3.6V
0.1μF
OF
CLKOUT+
CLKOUT–
D15
•
•
•
D0
OUTPUT
DRIVERS
CORRECTION
LOGIC AND
SHIFT REGISTER
AMPLITUDE (dBFS)
VCM
OGND
CLOCK/DUTY
CYCLE
CONTROL
3.3V
VDD
GND
0.1μF
0.1μF
0.1μF
22076 TA01
ENC+
ENC–
PGA
SHDN
DITH
MODE
OE
ADC CONTROL INPUTS
RAND
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0
10
30
40
20
FREQUENCY (MHz)
50
22076 G05
22076fc
1
