M
24AA01/02
1K 1.8V I2C™ Serial EEPROM
FEATURES
PACKAGE TYPES
• Single supply with operation down to 1.8V
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
- 3 µA standby current typical at 1.8V
• Organized as a single block of 128 bytes (128 x 8)
or 256 bytes (256 x 8)
• 2-wire serial interface bus, I2C™ compatible
• Schmitt trigger, filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz (1.8V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• ESD protection > 3,000V
• 1,000,000 ERASE/WRITE cycles guaranteed
• Data retention > 200 years
• 8-pin DIP or SOIC package
• Available for extended temperature ranges
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
VSS
4
5
SDA
A0
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
VSS
4
5
SDA
SOIC
24AA01/02
The Microchip Technology Inc. 24AA01 and 24AA02
are 1K bit and 2K bit Electrically Erasable PROMs. The
devices are organized as a single block of 128 x 8-bit
or 256 x 8-bit memory with a two wire serial interface.
Low-voltage design permits operation down to 1.8 volts
with standby and active currents of only 3 µA and 1 mA,
respectively. The 24AA01 and 24AA02 also have pagewrite capability for up to 8 bytes of data. The 24AA01
and 24AA02 are available in the standard 8-pin DIP
and 8-pin surface mount SOIC packages.
A0
24AA01/02
DESCRIPTION
PDIP
BLOCK DIAGRAM
WP
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
PAGE LATCHES
SDA
SCL
YDEC
VCC
VSS
SENSE AMP
R/W CONTROL
I2C is a trademark of Philips Corporation
© 1998 Microchip Technology Inc.
DS21052H-page 1
24AA01/02
TABLE 1-3:
AC CHARACTERISTICS
Standard Mode
Parameter
Symbol
Min
VCC = 4.5 - 5.5V
Fast Mode
Max
Min
Units
Remarks
Max
Clock frequency
FCLK
—
100
—
400
kHz
Clock high time
THIGH
4000
—
600
—
ns
Clock low time
TLOW
4700
—
1300
—
ns
TR
—
1000
—
300
ns
(Note 1)
SDA and SCL rise time
TF
—
300
—
300
ns
(Note 1)
START condition hold time
THD:STA
4000
—
600
—
ns
After this period the first
clock pulse is generated
START condition setup
time
TSU:STA
4700
—
600
—
ns
Only relevant for repeated
START condition
(Note 2)
SDA and SCL fall time
Data input hold time
THD:DAT
0
—
0
—
ns
Data input setup time
TSU:DAT
250
—
100
—
ns
STOP condition setup time
TSU:STO
4000
—
600
—
ns
Output valid from clock
TAA
—
3500
—
900
ns
(Note2)
Bus free time
TBUF
4700
—
1300
—
ns
Time the bus must be free
before a new transmission can start
Output fall time from VIH
min to VIL max
TOF
—
250
20 +0.1
CB
250
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppression (SDA and SCL pins)
TSP
—
50
—
50
ns
(Note 3)
Write cycle time
TWR
—
10
—
10
ms
Byte or Page mode
—
1M
—
1M
—
Endurance
cycles 25°C, Vcc = 5.5V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2:
BUS TIMING DATA
TR
TF
THIGH
TLOW
SCL
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
THD:STA
SCL
IN
TSP
TAA
THD:STA
TAA
TBUF
SDA
OUT
© 1998 Microchip Technology Inc.
DS21052H-page 3
