Standard Products UT1750AR RadHard RISC Microprocessor Data Sheet November 2000 FEATURES q Operates in either RISC (Reduced Instruction Set Computer) mode or MIL-STD-1750A mode q Built-in multiprocessor bus arbitration and Direct Memory Access support (DMA) q Supports MIL-STD-1750A 32-bit floating-point operations and 48-bit extended-precision floating-point operations on chip q TTL-compatible I/O q Built-in 9600 baud UART q Full military operating range, -55°C to +125°C, in accordance with MIL-PRF-38535 for Class Q and V q Stable 1.5-micron CMOS technology q Supports defined MIL-STD-1750A Console Mode of Operation q Typical radiation performance q Full 64K-word address space. Expandable to 1M words with optional MMU (operand port) - Total dose: 1.0E6 rads(Si) - SEL Immune . 100 MeV-cm2/mg - LETTH(0.25) = 60 MeV-cm 2/mg q Register-oriented architecture has 21 user-accessible registers - Saturated Cross Section (cm2) per bit, 1.2E-7 q Registers may be in 16-bit word or 32-bit double-word configurations BRQ BGNT BUSY BGACK NUI1 NUI2 M1750 TIMCLK TEST UARTOUT UARTIN UART BUS ARBITRATION IR TR 32 TEMP DEST BIT REG 32 TEMP SRC RISC MAP 16 FR PI 32 16 TB IM 16 ST SW SHIFT REG PROCESSOR CONTROL LOGIC TBR RBR GENERAL PURPOSE REGISTERS OSCILLATOR /CLOCK PROCESSOR STATUS STATE1 MME NUO3 CONSOLE q Standard Military Drawing 5962-01502 16 OSCOUT OSCIN SYSCLK RISC MEMORY CONTROL OE WE - 2.3E-11 errors/bit-day, Adams to 90% geosynchronous heavy ion 16 16 I/O MUX 16 16 32 RISC DATA MRST 32 8 RISC ADDRESS or O/P DISC RISC ADDRESS SYSFL BTERR MPAR MPROT PFAIL IOLINT1 IOLINT0 INT0-5 32 16 16 4 16 6 IC/ICs RISC ADD MUX I N T E R R U P T S ACC 32 PIPELINE 32 PR A MUX BUS CONTROL B MUX 16 32-BIT ALU 1750 SP 16 32 1750 PC 16 Figure 1. UT1750AR Functional Block Diagram ADDR MUX 4 PS0-3 AS0-3 OPERAND DATA OP/IN DTACK M/IO R/WR AS DS OPERAND ADDRESS




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