74ABT821
10-bit D-type flip-flop; positive-edge trigger; 3-state
Rev. 5 — 7 November 2011
Product data sheet
1. General description
The 74ABT821 high-performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT821 bus interface register is designed to eliminate the extra packages required
to buffer existing registers and provide extra data width for wider data/address paths of
buses carrying parity.
The 74ABT821 is a buffered 10-bit wide version of the 74ABT374A.
The 74ABT821 is a 10-bit, edge-triggered register coupled to ten 3-state output buffers.
The device is controlled by the clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of each D input, one set-up time before the
LOW-to-HIGH clock transition is transferred to the corresponding output Q of the flip-flop.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors.
The active LOW output enable (OE) controls all ten 3-state buffers independent of the
register operation. When OE is LOW, the data in the register appears at the outputs.
When OE is HIGH, the outputs are in high-impedance OFF-state, which means they will
neither drive nor load the bus.
2. Features and benefits
High-speed parallel registers with positive-edge triggered D-type flip-flops
Ideal where high speed, light loading, or increased fan-in are required with MOS
microprocessors
Output capability: +64 mA and 32 mA
Power-on 3-state
Power-on reset
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
74ABT821
NXP Semiconductors
10-bit D-type flip-flop; positive-edge trigger; 3-state
5. Pinning information
5.1 Pinning
74ABT821
OE
1
24 VCC
D0
2
23 Q0
D1
3
22 Q1
D2
4
21 Q2
D3
5
20 Q3
D4
6
19 Q4
D5
7
18 Q5
D6
8
17 Q6
D7
9
16 Q7
D8 10
15 Q8
D9 11
14 Q9
GND 12
13 CP
001aac733
Fig 4. Pin configuration
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
OE
1
output enable input (active LOW)
D0 to D9
2, 3, 4, 5, 6, 7, 8, 9, 10, 11
data input
GND
12
ground (0 V)
CP
13
clock pulse input (active rising edge)
Q0 to Q9
23, 22, 21, 20, 19, 18, 17, 16, 15, 14
data output
VCC
24
supply voltage
74ABT821
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 7 November 2011
© NXP B.V. 2011. All rights reserved.
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