TC74HCT138AP/AF
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74HCT138AP, TC74HCT138AF
3-to-8 Line Decoder
The TC74HCT138A is a high speed CMOS 3-to-8 LINE
DECODER fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL, NMOS and CMOS output voltage levels.
When the device is enabled, 3 Binary Select inputs (A, B and
C) determine which one of the outputs ( Y0 - Y7 ) will go low.
When enable input G1 is held low or either G2A or G2B is
held high, decoding function is inhibited and all outputs go high.
G1, G2A , and G2B inputs are provided to ease cascade
connection and for use as an address decoder for memory
systems.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
TC74HCT138AP
TC74HCT138AF
Features
•
High speed: tpd = 17 ns (typ.) at VCC = 5 V
•
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
•
Compatible with TTL outputs: VIH = 2 V (min)
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
VIL = 0.8 V (max)
•
Wide interfacing ability: LSTTL, NMOS, CMOS
•
Output drive capability: 10 LSTTL loads
•
•
Symmetrical output impedance: |IOH| = IOL = 4 mA (min)
∼
Balanced propagation delays: tpLH − tpHL
•
: 1.00 g (typ.)
: 0.18 g (typ.)
Pin and function compatible with 74LS138
Pin Assignment
Start of commercial production
1988-04
1
2014-03-01
