HD74HCT564, HD74HCT574
Octal D-type Flip-Flops (with 3-state outputs)
REJ03D0670–0200
(Previous ADE-205-560)
Rev.2.00
Mar 30, 2006
Description
These devices are positive edge triggered flip-flops. The difference between HD74HCT564 and HD74HCT574 is only
that the former has inverting outputs and the latter has noninvertering outputs.
Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs on positive
going transitions of the clock (CK) input. when a high logic level is applied to the output control (OC) input, all outputs
go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage
elements.
Features
•
•
•
•
•
•
•
LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
High Speed Operation: tpd (D to Q, Q) = 15 ns typ (CL = 50 pF)
High Output Current: Fanout of 15 LSTTL Loads
Wide Operating Voltage: VCC = 4.5 to 5.5 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
HD74HCT564P
PRDP0020AC-B
DILP-20 pin
P
(DP-20NEV)
HD74HCT574P
HD74HCT564FPEL
PRSP0020DD-B
SOP-20 pin (JEITA)
FP
(FP-20DAV)
HD74HCT574FPEL
HD74HCT564RPEL
PRSP0020DC-A
SOP-20 pin (JEDEC)
RP
(FP-20DBV)
HD74HCT574RPEL
Note: Please consult the sales office for the above package availability.
Package
Abbreviation
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
EL (1,000 pcs/reel)
Function Table
Inputs
Clock
Outputs
Output Control
Data
HD74HCT564
HD74HCT574
L
H
L
H
L
L
H
L
L
L
X
Q0
Q0
H
X
X
Z
Z
Q0 : level of Q before the indicated Steady-sate input conditions were established.
Q0 : complement of Q0 or level of Q before the indicated Steady-state input Conditions were established.
Rev.2.00 Mar 30, 2006 page 1 of 8
