MM74HC374 3-STATE Octal D-Type Flip-Flop
September 1983
Revised May 2005
MM74HC374
3-STATE Octal D-Type Flip-Flop
General Description
Features
The MM74HC374 high speed Octal D-Type Flip-Flops utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized
system.
s Typical propagation delay: 20 ns
s Wide operating voltage range: 2–6V
s Low input current: 1 PA maximum
s Low quiescent current: 80 PA maximum
s Compatible with bus-oriented systems
s Output drive capability: 15 LS-TTL loads
These devices are positive edge triggered flip-flops. Data
at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going
transitions of the CLOCK (CK) input. When a high logic
level is applied to the OUTPUT CONTROL (OC) input, all
outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the
storage elements.
The 74HC logic family is speed, function, and pinout compatible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Ordering Code:
Order Number
Package Number
MM74HC374WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC374SJ
MM74HC374MTC
MM74HC374N
MTC20
N20A
Package Description
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Truth Table
Pin Assignments for DIP, SOIC, SOP and TSSOP
Output
Clock
Data
Output
L
n
H
H
L
n
L
L
L
L
X
Q0
H
X
X
Z
Control
H HIGH Level
L LOW Level
X Don't Care
n Transition from LOW-to-HIGH
Z High Impedance State
The level of the output before steady state input conditions were
Q0
established
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© 2005 Fairchild Semiconductor Corporation
DS005336
www.fairchildsemi.com
