a
Microprocessor
Supervisory Circuits
ADM691A/ADM693A/ADM800L/M
FEATURES
Low Power Consumption:
Precision Voltage Monitor
؎2% Tolerance on ADM800L/M
Reset Time Delay—200 ms, or Adjustable
1 A Standby Current
Automatic Battery Backup Power Switching
Fast Onboard Gating of Chip Enable Signals
Also Available in TSSOP Package (ADM691A)
APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Automotive Systems
Critical P Power Monitoring
FUNCTIONAL BLOCK DIAGRAM
BATT ON
4.65V1
VCC
VOUT
VBATT
CHIP ENABLE
OUTPUT
CONTROL
The ADM691A/ADM693A/ADM800L/ADM800M family of
supervisory circuits offers complete single chip solutions for
power supply monitoring and battery control functions in
microprocessor systems. These functions include µP reset,
backup-battery switchover, watchdog timer, CMOS RAM write
protection, and power-failure warning. The family of products
provides an upgrade for the MAX691A/93A/800M family of
products.
All parts are available in 16-pin DIP and SO packages. The
ADM691A is also available in a space-saving TSSOP package.
The following functionality is provided:
1. Power-on reset output during power-up, power-down and
brownout conditions. The circuitry remains operational with
VCC as low as 1 V.
2. Battery backup switching for CMOS RAM, CMOS microprocessor or other low power logic.
3. A reset pulse if the optional watchdog timer has not been
toggled within a specified time.
4. A 1.25 V threshold detector for power fail warning, low battery detection, or to monitor a power supply other than +5 V.
CEOUT
CEIN
OSC IN
OSC SEL
RESET &
WATCHDOG
TIMEBASE
RESET &
GENERATOR
RESET
RESET
WATCHDOG
INPUT (WDI)
GENERAL DESCRIPTION
LOW LINE
WATCHDOG
TRANSITION DETECTOR
WATCHDOG
OUTPUT (WDO)
WATCHDOG
TIMER
POWER FAIL
INPUT (PFI)
POWER FAIL
OUTPUT (PFO)
1.25V
ADM691A/ADM693A
ADM800L/ADM800M
1VOLTAGE
INPUT
POWER
DETECTOR = 4.4V (ADM693A/ADM800M)
+5V
7805
0.1µF
VCC
CMOS
RAM
R1
VCC
VBATT
BATTERY
PFI
GND
R2
NC
BAT
ON
VOUT
CEOUT
ADM691A CEIN
ADM693A
ADM800L
ADM800M WDI
PFO
OSC IN
OSC SEL
LOW LINE
ADDRESS
DECODE
RESET
A0–A15 µP
POWER
I/O LINE
NMI
µP
RESET
WDO
SYSTEM
STATUS
INDICATORS
Figure 1. Typical Application
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
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Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
