a
FEATURES
All-In-One Synchronous Buck Driver
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Programmable Transition Delay
Synchronous Override Control
Undervoltage Lockout
Programmable Overvoltage Shutdown
V CC Good Signal Drives Auxiliary Circuits
Shutdown Quiescent Current < 10 A
APPLICATIONS
Mobile Computing CPU Core Power Converters
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
Dual MOSFET Driver
with Bootstrapping
ADP3410
FUNCTIONAL BLOCK DIAGRAM
VCC
ADP3410
VCCGD
4.4V
GND
BST
DRVH
SD
IN
DLY
CONTROL
AND
OVERLAP
PROTECTION
CIRCUIT
VCC
SW
VCC
OVPSET
DRVL
1.2V
SRMON
DRVLSD
PGND
The ADP3410 is a dual MOSFET driver optimized for driving
two N-channel FETs that are the two switches in the nonisolated synchronous buck power converter topology. Each of
the drivers is capable of driving a 3000 pF load with a 20 ns
propagation delay and a 30 ns transition time. One of the drivers
can be bootstrapped, and is designed to handle the high-voltage
slew rate associated with “floating” high-side gate drivers. The
ADP3410 has several protection features: overlapping drive
prevention (ODP), undervoltage lockout (UVLO) with performance specified at very low VCC levels, and overvoltage protection
(OVP) that can be used to monitor either the input or output.
Additional features include: programmable transition delay, a
synchronous drive override control pin, a synchronous drive
status monitor and, in conjunction with exiting from the UVLO
mode, a VCC Good (VCCGD) signal capable of driving a 10 mA
load. The quiescent current, when the device is disabled, is less
than 10 mA.
VBATT
5V
GENERAL DESCRIPTION
SD
TO PWM
CONTROLLER
VCC
VCCGD
ADP3410
BST
IN
DRVLSD
SRMON
OVPSET
DRVH
VOUT
SW
DRVL
DLY
GND
PGND
Figure 1. Typical Application Circuit
REV. A
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© Analog Devices, Inc., 2002