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ADSP-21160MKB-80

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仕様・特性

SHARC Digital Signal Processor ADSP-21160M/ADSP-21160N SUMMARY FEATURES High performance 32-bit DSP—applications in audio, medical, military, graphics, imaging, and communication Super Harvard architecture—4 independent buses for dual data fetch, instruction fetch, and nonintrusive, zero-overhead I/O Backward compatible—assembly source level compatible with code for ADSP-2106x DSPs Single-instruction, multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point computation units, each with a multiplier, ALU, shifter, and register file Integrated peripherals—integrated I/O processor, 4M bits on-chip dual-ported SRAM, glueless multiprocessing features, and ports (serial, link, external bus, and JTAG) 100 MHz (10 ns) core instruction rate (ADSP-21160N) Single-cycle instruction execution, including SIMD operations in both computational units Dual data address generators (DAGs) with modulo and bitreverse addressing Zero-overhead looping and single-cycle loop setup, providing efficient program sequencing IEEE 1149.1 JTAG standard Test Access Port and on-chip emulation 400-ball 27 mm × 27 mm PBGA package Available in lead-free (RoHS compliant) package 200 million fixed-point MACs sustained performance (ADSP-21160N) CORE PROCESSOR DAG1 8 x 4 x 32 DAG2 8 x 4 x 32 PROCESSOR PORT ADDR DATA ADDR DATA I/O PORT DATA ADDR DATA ADDR JTAG 6 TEST AND EMULATION PROGRAM SEQUENCER PM ADDRESS BUS DM ADDRESS BUS PM DATA BUS BUS CONNECT (PX) TWO INDEPENDENT DUAL-PORTED BLOCKS BLOCK 1 INSTRUCTION CACHE 32 x 48-BIT BLOCK 0 TIMER DUAL-PORTED SRAM DM DATA BUS IOD 64 32 EXTERNAL PORT IOA 18 ADDR BUS MUX 32 32 MULTIPROCESSOR INTERFACE 16/32/40/48/64 DATA BUS MUX 32/40/64 64 HOST PORT MULT DATA REGISTER FILE (PEX) 16 x 40-BIT BARREL SHIFTER ALU BARREL SHIFTER DATA REGISTER FILE (PEY) 16 x 40-BIT MULT DMA CONTROLLER IOP REGISTERS (MEMORY MAPPED) 6 SERIAL PORTS (2) CONTROL, STATUS AND DATA BUFFERS ALU 4 LINK PORTS (6) 6 60 I/O PROCESSOR Figure 1. Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

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