021
CY7C1021
64K x 16 Static RAM
Features
• High speed
— tAA = 12 ns
• CMOS for optimum speed/power
• Low active power
— 1320 mW (max.)
• Automatic power-down when deselected
• Independent Control of Upper and Lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
Functional Description
Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the write
enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O9 to I/O16. See the
truth table at the back of this data sheet for a complete description of read and write modes.
The CY7C1021 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power
consumption when deselected.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
The CY7C1021 is available in standard 44-pin TSOP Type II
and 400-mil-wide SOJ packages.
Logic Block Diagram
Pin Configuration
SOJ / TSOP II
Top View
SENSE AMPS
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
64K x 16
RAM Array
512 X 2048
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
I/O1 – I/O8
I/O9 – I/O16
COLUMN DECODER
A8
A9
A10
A11
A12
A13
A14
A15
BHE
WE
CE
OE
BLE
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
1021-2
Selection Guide
7C1021-10
Maximum Access Time (ns)
7C1021-12
7C1021-15
7C1021-20
10
Maximum Operating Current (mA)
Commercial
Maximum CMOS Standby Current (mA)
Commercial
L
12
15
20
220
220
220
220
5
5
5
5
0.5
0.5
0.5
0.5
Shaded areas contain preliminary information.
Cypress Semiconductor Corporation
Document #: 38-05054 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 24, 2001
