Advance Information
ICS9DS400
Four Output Differential Buffer for PCIe Gen 2 with Spread
General Description
Features/Benefits
The 9DS400 is pin compatible to the 9DB403, but adds the
ability to inject spread spectrum onto the incoming differential
clock, while maintaining good phase noise.
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Bypass mode
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Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Recommended Application
Output Features
DB400 where spread spectrum needs to be added to the
incoming clock.
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•
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Key Specifications
•
•
•
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Output cycle-cycle jitter < 50ps
Output to Output skew <50ps
Phase jitter: PCIe Gen1 < 86ps peak to peak
Phase jitter: PCIe Gen2 < 3.0/3.1ps rms
•
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4 - 0.7V current-mode differential output pairs.
Supports Spread Injection mode and fanout mode.
Two pin selectable down spread amounts: 0.5% and
0.25%.
50-110 MHz operation in PLL mode
50-400 MHz operation in Bypass mode
Functional Block Diagram
2
OE(6,1)#
Spread
Generating
PLL
SRC_IN
SRC_IN#
M
U
X
STOP
LOGIC
4
DIF(6,5,2,1))
DIF_STOP
SPREAD_EN
BYPASS#_SSCG
PD
SDATA
SCLK
CONTROL
LOGIC
IREF
Polarities shown assuming that OE_INV = 1
IDTTM/ICSTM Four Output Differential Buffer for PCIe Gen 2 with Spread
1626
1
09/17/09
