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Freescale Semiconductor
DSP56001
Freescale Semiconductor, Inc...
24-Bit General Purpose
Digital Signal Processor
Pin Grid Array (PGA)
Available in an 88 pin ceramic
through-hole package.
Ceramic Quad Flat Pack (CQFP)
The DSP56001 is a member of Motorola’s family of
Available in a 132 pin, small footprint,
HCMOS, low-power, general purpose Digital Signal
surface mount package.
Processors. The DSP56001 features 512 words of full
speed, on-chip program RAM (PRAM) memory, two
Plastic Quad Flat Pack (PQFP)
256 word data RAMs, two preprogrammed data
Available in a 132 pin, small footprint,
ROMs, and special on-chip bootstrap hardware to persurface mount package.
mit convenient loading of user programs into the program RAM. It is an off-the-shelf part since the program
memory is user programmable. The core of the processor consists of three execution units operating in parallel — the data ALU,
the address generation unit, and the program controller. The DSP56001 has MCU-style on-chip peripherals, program and data
memory, as well as a memory expansion port. The MPU-style programming model and instruction set make writing efficient, compact code, straightforward.
The high throughput of the DSP56001 makes it well-suited for communication, high-speed control, numeric processing, computer
and audio applications. The key features which facilitate this throughput are:
• Speed
At 16.5 million instructions per second (MIPS) with a 33 MHz clock, the DSP56001 can execute
a 1024 point complex Fast Fourier Transform in1.98 milliseconds (66,240 clock cycles).
• Precision
The data paths are 24 bits wide thereby providing 144 dB of dynamic range; intermediate results
held in the 56-bit accumulators can range over 336 dB.
• Parallelism
The data ALU, address arithmetic units, and program controller operate in parallel so that an instruction prefetch, a 24x24-bit multiplication, a 56-bit addition, two data moves, and two address
pointer updates using one of three types of arithmetic (linear, modulo, or reverse carry) can be
executed in a single instruction cycle. This parallelism allows a four coefficient Infinite Impulse Response (IIR) filter section to be executed in only four cycles, the theoretical minimum for a single
multiplier architecture.
• Integration
In addition to the three independent execution units, the DSP56001 has six on-chip memories,
three on-chip MCU style peripherals (Serial Communication Interface, Synchronous Serial Interface, and Host Interface), a clock generator and seven buses (three address and four data), making the overall system functionally complete and powerful, but also very low cost, low power, and
compact.
• Invisible Pipeline
The three-stage instruction pipeline is essentially invisible to the programmer thus allowing
straightforward program development in either assembly language or a high-level language such
as ANSI C.
• Instruction Set
The 62 instruction mnemonics are MCU-like making the transition from programming microprocessors to programming the DSP56001 digital signal processor as easy as possible. The orthogonal syntax supports control of the parallel execution units. This syntax provides 12,808,830 different instruction variations using the 62 instruction mnemonics. The no-overhead DO instruction
and the REPEAT (REP) instruction make writing straight-line code obsolete.
• DSP56000/DSP56001
The DSP56001 is identical to the DSP56000 except that it has 512x24-bits of on-chip program
RAM instead of 3.75K of program ROM; a 32x24-bit bootstrap ROM for loading the program RAM
from either a byte-wide memory mapped ROM or via the Host Interface; and the on-chip X and Y
Data ROMs have been preprogrammed as positive Mu- and A-Law to linear expansion tables and
a full, four quadrant sine wave table, respectively.
Compatibility
• Low Power
As a CMOS part, the DSP56001 is inherently very low power; however, three other features can
reduce power consumption to an exceptionally low level.
— The WAIT instruction shuts off the clock in the central processor portion of the DSP56001.
— The STOP instruction halts the internal oscillator.
— Power increases linearly (approximately) with frequency; thus, reducing the clock frequency
reduces power consumption.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
© MOTOROLA INC., 1992
May 4, 1998
