ispLSI 5512VA
®
In-System Programmable
3.3V SuperWIDE™ High Density PLD
Features
Functional Block Diagram
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Input Bus
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block
Input Bus
Input Bus
Input Bus
Input Bus
Generic
Logic Block
Generic
Logic Block
Generic
Logic Block
Input Bus
Generic
Logic Block
Generic
Logic Block
Global Routing Pool
(GRP)
Generic
Logic Block
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
Boundary
Scan
Interface
Input Bus
Input Bus
Input Bus
Generic
Logic Block
Generic
Logic Block
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 110 MHz Maximum Operating Frequency
— tpd = 8.5 ns Propagation Delay
— Enhanced tsu2 = 7 ns, tsu3 (CLK0/1) = 4.5ns,
tsu3 (CLK2/3) = 3.5ns
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path Optimization
Input Bus
Generic
Logic Block
Generic
Logic Block
Input Bus
Input Bus
Generic
Logic Block
Input Bus
• SuperWIDE HIGH-DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 24000 PLD Gates / 512 Macrocells
— Up to 288 I/O Pins
— 512 Registers
— High-Speed Global Interconnect
— SuperWIDE 32 Generic Logic Block (GLB) Size for
Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast
Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package Options
— Interfaces with Standard 5V TTL Devices
Input Bus
ispLSI 5000V Description
The ispLSI 5000V Family of In-System Programmable
High Density Logic Devices is based on Generic Logic
Blocks (GLBs) of 32 registered macrocells and a single
Global Routing Pool (GRP) structure interconnecting the
GLBs.
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports
up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Macrocell Registers Feature Multiple Control
Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell
Product Term Clocks
— Slew and Skew Programmable I/O (SASPI/O)
Supports Programmable Bus Hold, Pull-up, Open
Drain and Slew and Skew Rate Options
— Six Global Output Enable Terms, Two Global OE
Pins and One Product Term OE per Macrocell
Outputs from the GLBs drive the Global Routing Pool
(GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive
any or all the GLBs in the device. This mechanism allows
fast, efficient connections across the entire device.
Each GLB contains 32 macrocells and a fully populated,
programmable AND-array with 160 logic product terms
and five extra control product terms. The GLB has 68
inputs from the Global Routing Pool which are available
in both true and complement form for every product term.
The 160 product terms are grouped in 32 sets of five and
sent into a Product Term Sharing Array (PTSA) which
allows sharing up to a maximum of 35 product terms for
a single function. Alternatively, the PTSA can be bypassed for functions of five product terms or less. The
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
5512va_08
1
January 2002
