K7P403623M
K7P401823M
128Kx36 & 256Kx18 SRAM
Document Title
128Kx36 & 256Kx18 Synchronous Pipelined SRAM
Revision History
Rev. No.
History
Rev. 0.0
- Preliminary specification release
Rev. 0.1
- Change specification format.
No change was made in parameters.
April, 1997
Preliminary
Rev. 0.2
- Updated Part Number and Pin Description.
Updated and added Input/Output Voltage Level and VDDQ
Updated DC Characteristics and Pin Capacitance.
Updated AC Characteristics, Test Conditions and Timing Wave Form.
For JTAG, updated Vendor Definition and added tSVCH/tCHSX.
Jan. 1998
Preliminary
Rev. 0.3
- Updated PECL Clock Input Level, Output Leakage Current
Updated 119BGA Package Thermal Characteristics
Aug. 1998
Preliminary
Rev. 1.0
- Final specification release
Dec. 1998
Final
Rev. 2.0
- Single ended LVCMOS clock operation added
Oct. 2000
Draft Date
Remark
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
-1-
Oct. 2000
Rev 2.0
