MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1:4 Clock Distribution Chip
MC10EL15
MC100EL15
The MC10EL/100EL15 is a low skew 1:4 clock distribution chip
designed explicitly for low skew clock distribution applications. The
device can be driven by either a differential or single-ended ECL or, if
positive power supplies are used, PECL input signal. If a single-ended
input is to be used the VBB output should be connected to the CLK input
and bypassed to ground via a 0.01µF capacitor. The VBB output is
designed to act as the switching reference for the input of the EL15 under
single-ended input conditions, as a result this pin can only source/sink up
to 0.5mA of current.
The EL15 features a multiplexed clock input to allow for the distribution
of a lower speed scan or test clock along with the high speed system
clock. When LOW (or left open and pulled LOW by the input pulldown
resistor) the SEL pin will select the differential clock input.
16
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
The common enable (EN) is synchronous so that the outputs will only
be enabled/disabled when they are already in the LOW state. This avoids
any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock, therefore
all associated specification limits are referenced to the negative edge of
the clock input.
•
•
•
•
•
50ps Output-to-Output Skew
Synchronous Enable/Disable
PIN DESCRIPTION
Multiplexed Clock Input
PIN
75kΩ Internal Input Pulldown Resistors
>1000V ESD Protection
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
VCC
EN
16
SCLK CLK
15
14
CLK
SEL
11
10
9
CLK
SCLK
EN
SEL
VBB
Q0–3
Diff Clock Inputs
Scan Clock Input
Sync Enable
Clock Select Input
Reference Output
Diff Clock Outputs
VEE
12
13
VBB
FUNCTION
FUNCTION TABLE
CLK
0
D
Q
1
2
3
4
5
6
7
8
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
SCLK
SEL
EN
Q
L
H
X
X
X
1
X
X
L
H
X
L
L
H
H
X
L
L
L
L
H
L
H
L
H
L*
* On next negative transition of
CLK or SCLK
5/95
© Motorola, Inc. 1996
3–1
REV 2
