MC10162
Binary to 1-8 Decoder
(High)
The MC10162 is designed to convert three lines of input data to a
one–of–eight output. The selected output will be high while all other
outputs are low. The enable inputs, when either or both are high, force
all outputs low.
The MC10162 is a true parallel decoder. No series gating is used
internally, eliminating unequal delay times found in other decoders.
This device is ideally suited for demultiplexer applications. One of
the two enable inputs is used as the data input, while the other is used
as a data enable input.
A complete mux/demux operation on 16 bits for data distribution is
illustrated in Figure 1 of the MC10161 data sheet.
• PD = 315 ns typ/pkg (No Load)
• tpd = 4.0 ns typ
• tr, tf = 2.0 ns typ (20%–80%)
http://onsemi.com
MARKING
DIAGRAMS
16
CDIP–16
L SUFFIX
CASE 620
MC10162L
AWLYYWW
1
16
PDIP–16
P SUFFIX
CASE 648
MC10162P
AWLYYWW
1
LOGIC DIAGRAM
1
E0Ą2
E1Ą15
PLCC–20
FN SUFFIX
CASE 775
6ĄQ0
5ĄQ1
10162
AWLYYWW
4ĄQ2
AĄ7
A
WL
YY
WW
3ĄQ3
13ĄQ4
BĄ9
= Assembly Location
= Wafer Lot
= Year
= Work Week
12ĄQ5
DIP PIN ASSIGNMENT
11ĄQ6
VCC1
16
VCC2
2
15
E1
Q3
3
14
C
Q2
4
13
Q4
Q1
5
12
Q5
Q0
10ĄQ7
1
E0
CĄ14
6
11
Q6
A
7
10
Q7
VEE
8
9
B
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
TRUTH TABLE
INPUTS
OUTPUTS
E0
E1
C
B
A
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
X
H
L
L
L
L
H
H
H
H
X
X
L
L
H
H
L
L
H
H
X
X
L
H
L
H
L
H
L
H
X
X
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
H
L
L
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion Tables
on page 18 of the ON Semiconductor MECL Data Book
(DL122/D).
ORDERING INFORMATION
CDIP–16
25 Units / Rail
PDIP–16
25 Units / Rail
MC10162FN
1
Shipping
MC10162P
January, 2002 – Rev. 7
Package
MC10162L
© Semiconductor Components Industries, LLC, 2002
Device
PLCC–20
46 Units / Rail
Publication Order Number:
MC10162/D
