MC10H334
Quad Bus Driver/Receiver
with Transmit and Receiver
Latches
The MC10H334 is a Quad Bus Driver/Receiver with transmit and
receiver latches. When disabled, (OE = high) the bus outputs will fall
to −2.0 V. Data to be transmitted or received is passed through its
respective latch when the respective latch enable (DLE and RLE) is at
a low level. Information is latched on the positive transition of DLE
and RLE. The parameters specified are with 25 Ω loading on the bus
drivers and 50 Ω loads on the receivers.
• Propagation Delay, 1.6 ns Typical Data−to−Output
• Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range)
• Voltage Compensated
• MECL 10K−Compatible
http://onsemi.com
MARKING
DIAGRAMS
20
CDIP−20
L SUFFIX
CASE 732
MC10H334L
AWLYYWW
1
20
PDIP−20
P SUFFIX
CASE 738
DIP & PLCC
PIN ASSIGNMENT
MC10H334P
AWLYYWW
1
1
VCC
1
20
VCC03
BUS1
2
19
BUS2
BUS0
3
18
BUS3
VCC02
4
17
OE
D1
5
16
D2
D0
6
15
D3
DLE
7
14
RLE
R0
8
13
R3
R1
9
12
10
11
A
WL
YY
WW
10H334
AWLYYWW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
R2
VEE
PLCC−20
FN SUFFIX
CASE 775
VCC02
Device
Shipping
MC10H334L
Pin assignment is for Dual−in−Line Package.
For PLCC pin assignment, see the Pin Conversion Tables on page 18
of the ON Semiconductor MECL Data Book (DL122/D).
Package
CDIP−20
18 Units/Rail
MC10H334P
PDIP−20
18 Units/Rail
MC10H334FN
PLCC−20
46 Units/Rail
NOTE:
Each MECL 10H series circuit has been designed
to meet the dc specifications shown in the test table,
after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed
circuit board and transverse air flow greater than
500 Ifpm is maintained. Receiver outputs are
terminated through a 50−ohm resistor to −2.0 volts
dc. Bus outputs are terminated through a 25−ohm
resistor to −2.0 volts dc.
© Semiconductor Components Industries, LLC, 2000
March, 2000 − Rev. 6
130
Publication Order Number:
MC10H334/D
