MC10H641, MC100H641
Single Supply PECL to TTL
1:9 Clock Distribution Chip
Description
The MC10H/100H641 is a single supply, low skew translating 1:9
clock driver. Devices in the ON Semiconductor H641 translator series
utilize the PLCC−28 for optimal power pinning, signal flow through
and electrical performance.
The device features a 24 mA TTL output stage, with AC
performance specified into a 50 pF load capacitance. A latch is
provided on−chip. When LEN is LOW (or left open, in which case it is
pulled LOW by the internal pulldown) the latch is transparent. A
HIGH on the enable pin (EN) forces all outputs LOW. Both the LEN
and EN pins are positive ECL inputs.
The VBB output is provided in case the user wants to drive the
device with a single−ended input. For single−ended use, the VBB
should be connected to the D input and bypassed with a 0.01 mF
capacitor.
The 10H version of the H641 is compatible with positive
MECL 10H™ logic levels. The 100H version is compatible with
positive 100K levels.
http://onsemi.com
PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1
Features
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PECL − TTL Version of Popular ECLinPS E111
Low Skew
Guaranteed Skew Spec
Latched Input
Differential ECL Internal Design
VBB Output for Single−Ended Use
Single +5.0 V Supply
Logic Enable
Extra Power and Ground Supplies
Separate ECL and TTL Supply Pins
Pb−Free Packages are Available*
MCxxxH641G
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev.7
1
Publication Order Number:
MC10H641/D
