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by MCM6706B/D
SEMICONDUCTOR TECHNICAL DATA
MCM6706B
Product Preview
32K x 8 Bit Static Random
Access Memory
28
The MCM6706B is a 262,144 bit static random access memory organized as
32,768 words of 8 bits. Static design eliminates the need for external clocks or
timing strobes.
Output enable (G) is a special control feature that provides increased system
flexibility and eliminates bus contention problems.
The MCM6706B is available in a 300 mil, 28–lead surface–mount SOJ
package.
•
•
•
•
•
Single 5.0 V ± 10% Power Supply
Fully Static — No Clock or Timing Strobes Necessary
All Inputs and Outputs Are TTL Compatible
Three State Outputs
Fast Access Times: MCM6706B–8 = 8 ns
MCM6706B–10 = 10 ns
MCM6706B–12 = 12 ns
J PACKAGE
300 MIL SOJ
CASE 810B–03
1
PIN ASSIGNMENT
A
28
VCC
2
27
W
A
3
26
A
A
4
25
A
A
5
24
A
A
6
23
A
A
7
22
G
A
BLOCK DIAGRAM
1
A
8
21
A
A
9
20
E
A
A
10
19
DQ
A
DQ
11
18
DQ
DQ
12
17
DQ
DQ
13
16
DQ
VSS
14
15
DQ
A
A
A
ROW
DECODER
MEMORY MATRIX
(256 ROWS
128 x 8 COLUMNS)
A
A
A
PIN NAMES
DQ
COLUMN I/O
COLUMN DECODER
INPUT
DATA
CONTROL
DQ
A
A
A
A
A
A
A
A . . . . . . . . . . . . . . . . . . . . Address Input
W . . . . . . . . . . . . . . . . . . . . Write Enable
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
DQ . . . . . . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . + 5.0 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
E
W
G
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 1
10/9/96
© Motorola, Inc. 1996
MOTOROLA FAST SRAM
MCM6706B
1
